Using Synopsys FPGA Compiler

FPGA Compiler is the Synopsys "Design Compiler" synthesizer with added features that produce circuits optimized for FPGA architectures. You can use either the command-line interface directly ("fpga_shell") or a graphical front-end ("fpga_analyzer"). The instructions below are only for fpga_shell.

Preliminary Steps

  1. Make sure you have added the lines to your .cshrc.local file that add the Synopsys directories to your path as described in the instruction on using Design Compiler. In addition, add the following two lines to your .cshrc.local file to make the Xilinx place-and-route software available: 
    setenv XACT /usr/applic/XSI
setenv PATH ${XACT}/bin/sparc:${PATH}
    (then log out and back in or type exec csh to set up the paths for the first time).
  2. Create a new directory where you will put your FPGA designs (the command to do this is mkdir dirname). This directory should be different than the one you used for the previous VHDL exercises because you will need a new setup file.
  3. Create a file called .synopsys_dc.setup in this new directory containing the following lines: 
    designer = "NAME" ;
company  = "UBC EE";
plot_command = "lpr -P PRINTER" ;

search_path = { . \
        /usr/applic/XSI/synopsys/libraries/syn \
        /usr/applic/synopsys/libraries/syn }

link_library = { "*" xprim_4003-6.db xprim_4000-6.db xgen_4000.db \
        xio_4000a-6.db xfpga_4000-6.db }

target_library = { xprim_4003-6.db xprim_4000-6.db xgen_4000.db \
        xio_4000a-6.db xfpga_4000-6.db }

symbol_library = { xc4000.sdb }

synthetic_library = { xblox_4000.sldb }

define_design_lib xblox_4000 -path \
        /usr/applic/XSI/synopsys/libraries/dw/lib/fpga/xc4000

define_design_lib WORK -path ./WORK

compile_fix_multiple_port_nets = true

bus_naming_style = "%s<%d>"
bus_dimension_separator_style = "><"
bus_inference_style = "%s<%d>"

xnfout_library_version = "2.0.0"
    Note that the period at the start of the file name makes it invisible to a normal "ls" command. You can either cut and paste the lines above or make a copy using the command 
            cp ~elec464/fpga/.synopsys_dc.setup .
  4. Edit this file and change NAME to your name and change PRINTER to the name of the printer you will be using to print out the schematics. For example, the printer in the VLSI lab is called "vp1".
  5. In the new directory create a sub-directory called WORK where the Synopsys tools will place various work files.

Using FPGA Shell

To run the command-line interface, use the command: 
        fpga_shell
Then to read your VHDL file and check for errors (assuming it's called asg3.vhd) use the command: 
        read -f vhdl asg3.vhd
If your design has syntax errors, edit the source file to correct the errors and use the read command again. You will need to add "pads" (I/O buffer circuits) to the ports in your design. To do this use the commands: 
        set_port_is_pad "*"
        insert_pads
To compile your VHDL description into an optimized hardware description use the command: 
        compile
If you want to see what fraction of the FPGA's resources your design uses and the estimated propagation delay from the inputs to the outputs you can use the commands: 
        report_fpga
        report_timing
The circuit will have been synthesized using CLBs. Unfortunately, the Xilinx place-and-route software can only accept a gate-level circuit description. To convert the CLB-level design to a gate-level netlist use the command: 
        replace_fpga
To plot a schematic (before and/or after the replace_fpga command) use the commands: 
        create_schematic
        plot
You can now write out the gate-level circuit in XNF (Xilinx netlist format) using the commands: 
        write -format xnf -hierarchy -output asg3.sxnf
Note that the output file name has an .sxnf (not .xnf) extension.

Now you can exit fpga_shell and run the Xilinx place-and-route tools. This requires various steps which are executed under the control of the "xmake" program: 

        xmake -P 4003APC84-6 asg3
The -P option specifies the device into which the design will be loaded. In this case it's a 6-ns grade XC4003A packaged in an 84-pin PLCC.

The programs run by xmake will create lots of small files and reports in your directory. The final result is the "asg3.bit" file that contains the configuration information that must be loaded into the FPGA at power-up to configure it.

Downloading the Configuration File

Make sure that the demo board power supply is turned on, that the serial cable is plugged into either of the two serial connectors (ttya or ttyb) on the back of the workstation and that the configuration DIP switches SW1 and SW2 on the demo board are set properly: 
   switch      SW1      SW2
     1          X        X      
     2          X       off
     3          X       off
     4          X       on 
     5          X       on
     6          X       on
     7         off       X
     8         off      off
where X is "don't care." Use the following command to download the configuration file to the FPGA (assuming the file name is asg3.bit): 
        xchecker asg3.bit
The xchecker program will first check to make sure the demo board is hooked up. Then it will print a prompt and wait for you to press Enter. It will then attempt to download the configuration (.bit) file.

Hints

Run Times

Synthesis and place-and-route tools have a well-deserved reputation for being slow and memory-intensive. Run times of 10 minutes for our small designs and several hours for more typical ones are common. Make sure your design simulates properly before starting synthesis and allow plenty of time to complete the assignment.
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