Using Design Compiler

Using Synopsys Design Compiler

The process of converting a VHDL description to a hardware design is called "synthesis." We will use the "Design Compiler" program from Synopsys. You can use either the command-line interface directly ("dc_shell") or a graphical front-end ("design_analyzer").

Preliminary Steps

Add the following lines to the file .cshrc.local in your home directory. They will add the Synopsys directories to your path every time you start a new shell.
```
set synpath = `echo $PATH | grep synopsys`
if ( $synpath == "" && -r /usr/common/Cshrc.synopsys ) then
  source /usr/common/Cshrc.synopsys
endif
unset synpath
```
(then log out and back in or type exec csh to set up the paths for the first time).
Create a new directory where you will put your VHDL files (the command to do this is mkdir dirname).

Create a file called .synopsys_dc.setup in this new directory containing the following lines:

designer = "NAME" ;
company  = "UBC EE";

search_path = { . /usr/applic/synopsys/libraries/syn };

link_library   = { class.db }
target_library = { class.db }
symbol_library = { class.sdb }

define_design_lib work -path ./WORK;

plot_command       = "lpr -P PRINTER" ;

Note that the period at the start of the file name makes it invisible to a normal "ls" command. You can either cut and paste the lines above or make a copy using the command

	cp ~elec464/.synopsys_dc.setup .

Edit this file and change NAME to your name and change PRINTER to the name of the printer you will be using to print out the schematics. For example, the printer in the VLSI lab is called "vp1".
In the new directory create a sub-directory called WORK where the Synopsys tools will place various work files.

Using DC Shell

To run the command-line interface, use the command:

	dc_shell

Then to read your VHDL file and check for errors (assuming it's called asg1.vhd) use the command:

	read -f vhdl asg1.vhd

If your design has syntax errors, edit the source file to correct the errors and use the read command again. To compile your VHDL description into an optimized hardware description use the command:

	compile

To create a schematic and plot it use the commands:

	create_schematic
	plot

To get help on any command use the command help followed by the command name. For example, to find out how to send the schematic to a file instead of the printer, use the command:

	help plot

Using Design Analyzer

To run the graphical interface enter the command:

	design_analyzer

To read your file and check it for errors:

select the File->Read menu item
select the name of your VHDL source file
click on OK

If your design has syntax errors, correct the errors and repeat the previous step.

To compile into an optimized design:

click on the Y=A+B icon to select it (the border becomes highlighted)
select the Tools->Design-Optimization menu item
click on OK

To view the schematic and plot it:

double-click on the Y=A+B icon to see your design's symbol
double-click on your design's symbol to see its schematic
select the File->Plot menu item
click on OK

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