Old Items

• Welcome back! Please check this page regularly for announcements.
• There will be no tutorial on Friday September 5.
• Students who do not have an account on the EE department's Unix network should contact Rob Ross to get one. You will need this account to do your first Assignment.
• Sources of information about VHDL on the Internet
• How to use the VHDL synthesis software
• Last year'sELEC 464 Web pages
• The Synopsys software setup is broken again. Please send complaints to the system administrator, Roozbeh Mehrabadi roozbeh@ece, since I can't do anything about it. The due date for Assignment 1 will be postponed. I'll post the new due date here when the problem is fixed.
• The Synopsys software setup is fixed. The due date for Assignment 1 has been postponed to Thursday, September 19 (any time on Thursday is fine). Hand in the solution to the assignment box near Room 332. The solutions will be posted on Friday.
• Overhead slides (Postscript format) for Ayman's VHDL tutorial: text (30 pages), and figures: page 1, page 2, page 3, page 4 (figures from Rushton).
• How to use the 8088 assembler
• How to use the VHDL simulation software
• Partial 74'161 data sheets in Postscript format from Philips (3 pages), Motorola (2 pages), and National (1 page, uses different pin names).
• You may submit Assignment 2 either electronically or using print-outs or both. For future assignments you may not have a choice so you might want to read the instructions on how to hand in files now and give it a try. The keys to use are:

      2q1log  - the output of the simulation run
      2q1ps   - the schematic of the synthesized circuit
  	      (use "plot -output design.ps" to generate the file)
      2q1vhd  - your VHDL code
      2q2asm  - the 8088 assembly language file
      2q2out  - the output from running the .COM file
  

• I'd like to find out how many people would prefer to submit assignments electronically. Please select one of the options below and Vote. As always, you can e-mail more detailed comments to edc@ece.ubc.ca.
  I would rather: hand in print-outs submit files electronically
  (Once only, please)
  The vote is over. The final results were: 11 prefer hard-copy submissions, 10 prefer electronic submissions.
• Synthesis for Xilinx FPGAs
• FPGA demo boards have been connected to the workstations ``kings'' and ``avalanche.'' The switch is not debounced so the display sometimes skips a state.
• There is a mistake in the LED segment table in Assignment 3. The value of segment 'g' for the digit '8' should be a 1. The testbench is correct.
• Please do not convert source code files to Postscript when submitting them electronically
• For simulation, VHDL initializes variables to their minimum value. In case of bit or bit_vectors this is 0. In general, initialization is not possible with synthesis, but in the specific case of FPGA flip-flops you can assume that they will be initialized to zero during configuration.
• The action for otherwise unspecified values in a VHDL case statement is specified as follows:

  when others => sequential statement

  for example:

  	when others => nextc <= "0000" ;
  

• If you have questions about the assignments, try the following (in decreasing order of preference):
  • ask one of the other students
  • read the manual (the VHDL compiler reference manual is available in the VLSI lab and most tools have on-line help)
  • post your question to the ee.elec464 newsgroup
  • ask me at the beginning of a lecture
  • ask me during office hours
  • e-mail me
  But please don't ask the TA unless it's a question about how your assignment was marked.
• To make sure other students are not tempted to read your assignments, you should probably remove read and search permissions on the relevant directories. You can do this with the chmod command (e.g. cd to the directory and type ``chmod go-rx .'').
• Overhead slides (Postscript format) for Ayman's second VHDL tutorial..
• How Assignment 1 was marked.
• The assignment 3 due date has been postponed to Monday, October 7.
• The mid-term exam will be 50 minutes long, open-book (any combination of notes, books and calculators is allowed), and will cover the material up to the lecture of October 22.
• There will be no tutorial on Friday, October 4.
• The tutorial on Friday October 11 will be on timing analysis (Assignment 4).
• The course newsgroup has changed. You should now be able to access it from most UBC news servers.
• Although the timing specification t_AVAV is shown on timing diagrams as the time from one valid address to the next valid address it actually refers to the cycle time (typically an integral number of clock periods).
• For Assignment 4 you may assume a perfect 1:2 clock duty cycle (tCLCH=133 ns and tCHCL=66 ns). You need not verify the 5 requirements for the CLK signal (period, low, high, rise and fall times).
• In Assignment 4, Question 2 the MCM6290 should be identified as a 16k by 4 RAM, not a 16 kB by 4 RAM (the data sheet is correct).
• On Friday October 18 Ayman will give a tutorial on image compression techniques and hardware (this is his research area so it should be interesting).
• Ayman has a bad cold so his talk has been postponed to November 1. The tutorial on October 18 will be on timing analysis (again) and memory design (Assignment 5).
• Your answer to question 3 in assignment 5 may also make use of any number of inverters to implement the SSI decoder.
• How Assignment 2 was marked.
• How Assignment 3 was marked.
• In question 2 of assignment 5 the EPROM start address should be F0000h instead of F8000h because the circuit is supposed to have 64kB of EPROM (see the posting on the newsgroup).
• If you have questions about how your assignment was marked, please ask the relevant TA first: Ayman (aymane@ece.ubc.ca) for Assignments 1 to 3, Anwar (anware@ece.ubc.ca) for Assignments 4 and 5. If you still have questions after talking to the TA then please ask me.
• The lecture on Thursday, October 24 will be a review lecture. A list of generic questions that might be on the mid-term exam will be provided.
• Please see the corrections for the solutions to Assignment 4 on the corrections page.
• How Assignment 4 was marked.
• How Assignment 5 was marked.
• I apologize for missing the tutorial on Friday. For some unknown reason I thought it was scheduled for 4:30 instead of 3:30 and so I showed up an hour late...

  I'll be available in my office all day on Monday October 28 to answer questions. Feel free to e-mail me your questions as well and I'll post any replies that might be of general interest.

• Important: you must decide how you will do the microcontroller assignment and register your group by 5:00 PM on Thursday, October 31.
• Solutions to the mid-term exam review.
• The answer to the first part of question 5 has been corrected.
• The VHDL code in question 2 has been corrected. 't' has been changed from 'bit' to 'bit_vector'.
• The mid-term will be held on Tuesday, October 29
• Assignments that are submitted late will be given a mark of zero. It doesn't matter when the assignment was completed.

  You should also realize that file time stamps or dates on printouts are very weak evidence that an assignment was completed on time since the file modification dates and the contents of Postscript files can be easily changed.

• How Assignment 6 was marked.
• Note the following corrections/clarifications to Assignment 7:
  • The vertical dashed line in the Refresh Cycle timing diagram is drawn half a clock period too early -- the refresh bus cycle ends on the falling edge of the clock.
  • The timing diagram shows the RFRSH signal as lasting only one clock cycle. It should extend for two clock cycles as described in the text.
  • Your design may assume that HOLDA will always be asserted in response to a HOLD request (i.e. you may ignore the CPU's HOLDA output).
  • The row address should be the MS 10 bits of the address and the column address should be the LS 10 bits of the address.
  • If AVALID is asserted and RFRSH is not asserted on the rising edge of the clock your circuit should assume that the CPU is doing a read cycle. This will allow the circuit to synchronize itself to the CPU state.
  • The electronic submission keys are given in the wrong order. They should be:

    VHDL code               7vhd
    Synthesized schematic   7ps
    Simulation output       7log
    

• The test-bench for Assignment 7 is in ~elec464/asg7tb.vhd. This test-bench runs 3 bus cycles (read, refresh and read).
• A corrected and more detailed timing diagram for Assignment 7 is available in Postscript format.
• A bug in the submit script prevented Postscript files from being submitted. It works now.
• Please do not e-mail me your assignments.

  The submit script will now try to submit a file even if it fails the sanity checks. If the submission fails you will be allowed to re-submit the same file as long as the checksum was e-mailed on time.

  If for some reason you need to e-mail me a large file please send it to the course ID: elec464@ece.ubc.ca and tell me about it.

• The course documents have been converted to PDF format.
• The 8051 compiler for Assignment 8 is available from ~elec464/51demo.exe. The sample code is available in ~elec464/asg8.c and the compiled result that you can program into the microcontroller is available in ~elec464/asg8.hex.
• The due date for Assignment 8 has been extended until 5:30 PM Wednesday, November 20 because of the late delivery of parts. Completed assignments can be submitted to me on Tuesday or to Ayman on Wednesday (details TBA).
• The total cost of the parts supplied for Assignment 8 was $6.56 (quantity 50).
• You can hand in Assignment 8 to Anwar Elfeitori (anware@ece.ubc.ca). He will be in his office in CISCR 267 at 12:30 and 5:30 pm.
• You can also hand in Assignment 8 to Ayman El-Nagar (aymane@ece.ubc.ca). He will be in his office in CISCR at 12:30 and in the VLSI lab at 5:30 pm.
• How Assignment 7 was marked.
• There will be no tutorial on Friday, November 21.
• How the mid-term exam was marked.
• The parts used in Assignment 8 will be returned to the EE inventory and be available for use in other courses and for system lab projects. You can purchase the microcontrollers from distributors (see the Atmel's web page for a list).
• If you have a concern about how your mid-term was marked, please attach a note to your exam and return it to me. I will re-mark that question (and possibly others).
• Please check your mid-term exam mark to make sure it was entered correctly.
• An Epson dot matrix printer with a parallel interface has been attached to a PC in room 322 (the same PC that you used to program the microcontrollers). You can use this PC to test your parallel printer port driver program. Do not use this PC for programming or debugging.

  Please:

  • only use the other computers during open lab sessions (check the schedule on the door)
  • don't leave any files on the hard disks of *any* of the computers (an editor, the assembler and linker will easily fit on one floppy disk).
• Note that the Centronics printer interface BUSY status bit is buffered through an inverter. When the printer is busy the following will be true:
  • the BUSY signal is HIGH
  • bit 7 of the status port is 0 (BUSY*)
• The AntiCMOS virus was found on a floppy used in room 322. There is a reasonable chance that any floppy you used on a machine in room 322 will have been infected.
  • If you boot from an infected floppy you will infect this new machine's hard disk.
  • This virus will erase the contents of a PC's CMOS setup memory when the machine boots up at some point in the future.
  • If you put a floppy on a machine that has this virus it will probably get infected.
  • You can detect and remove the virus by scanning the boot sector with virus-scanning software such as ~elec464/fp-224c.zip(780kB).
• How Assignment 8 was marked.
• How Assignment 9 was marked.
• Solutions for Exercises on Final Review Lecture, and schematic for Question 3.
• The final exam is scheduled for December 16 at 3:30 PM in MCML 166.
• Office hours during the exam period:
  • Friday December 6 from 9:30 to 12:30 AM
  • Friday December 13 from 9:30 to 12:30 AM
  • Friday December 13 from 1:30 to 5:30 PM
• Please check your assignment and mid-term marks. Report problems with assignment marks to the relevant TA: Ayman El-Nagar (aymane@ece.ubc.ca) for assignments 1, 2, 3, and 8, and Anwar Elfeitori (anware@ece.ubc.ca) for the others. Report problems with mid-term marks to me.
• The exam and solutions are available with the lecture notes.
• How the final exam was marked.