ELEC 464 - Marking of Final Exam

How the Final Exam Was Marked

Question 1

Question 1 was marked out of 20. Two marks were assigned for each of the following:

(a)

having 6 (or more) states

these states uniquely encoded (with 1 and 0 unless the VHDL code includes a declaration of the symbolic states)

progression through 5 states on '1' inputs

common transitions to one state on '0' inputs

output of '1' for all states except the state after five '1's and '0' otherwise. No marks were awarded for this part if the two tables were combined.

(b)

declaration of temporary signals for current and next state

"combinational" process that is sensitive to current state and data

process sets next state correctly for '0' and '1' inputs

process (sensitive to current state if a separate process) that sets the current output or a next-output signal according to current state

"sequential" process, sensitive to next state and clock, that sets the value of the current state and optionally the current output. Resetting the state to an all-zero (or all-ones) value on a clock edge when the `data' input is '1' or '0' was also allowed because this can be instantiated by Design Compiler as a synchronous reset/preset control with some logic libraries. No marks were awarded for this part if the results of the process depended on the current state because this would require combinational logic.

Question 2

Question 2 was marked out of 18 as follows:

1, 1, 3, 3, 1, and 2 marks respectively for each of the six expressions. No partial marks for any incorrect expression except that only 1 mark was deducted if the solution used the sum of PWEH and PWEL rather than tcyc (this is not correct as explained in the solutions to Assignment 4). (total of 11)
1 mark for computing each numerical margin correctly according to the expression (total of 6).
1 mark for having all met/not-met (Y/N) decisions correct (total of 1)

Question 3

Question 3 was marked out of 12. Two marks were assigned for each of the following:

4 RAM chips
decoder input is A[15:13]
CS* driven by Y3* and Y2* (or Y2* and Y6* if in reverse order)
RAM address inputs are A[0:12]
RAM data inputs are D[0:3] and D[4:7]
each pair of RAMs selected by each CS has D[0:3] and D[4:7]

Question 4

Question 4 was marked out of 14. 1 or 2 marks were subtracted for each mistake. One mark was subtracted for simple mistakes. Two marks were subtracted for serious mistakes such as including code to test whether the character was printable, including delay loops, and infinite loops. If a major function was missing one mark was subtracted per line of code that would be required to implement the missing portion of the solution (14 marks in total according to the solution).

Common mistakes included:

using mov instead of in and out instructions

using

        in      al,03FEH

instead of

        mov     dx,03FEH
        in      al,dx

loading the I/O address from a vector at 0:03F8 instead of using the I/O address directly
using the wrong bit-mask with AND instruction to test bit 5 (mask should be 32, 20H or 00100000B)
using wrong type of conditinal branch (JNZ instead of JZ)
not saving the value of al (or whatever register contains the character) before using it to test the busy bit

Many people wrote programs that sent the null character terminating the string to the serial port. Although marks were not subtracted for doing this, the null character was the string terminator and should have not be transmitted.

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