Marking of Assignment 7
Only Question 1 was marked. It was marked out of 7:
- Four marks were awarded for submitting a design, one mark for
each of the following:
- submitting a VHDL file as long as it looked like an attempt
at this assignment
- the VHDL file having name, student number, date, and a few
comments
- a simulation log file
- a schematic of the synthesized design
- Up to 3 marks were awarded for correct behaviour as
demonstrated by the simulation log. One mark was subtracted for
each error (as shown by an ERROR message in the simulation log)
with a maximum deduction of -3. For example, if your simulation
log contained one ERROR message you would receive 2 marks for
this part.
Zero marks will be awarded for the assignment if the simulation
log is found not to correspond to the output generated by your
VHDL code. If this is the case you will be notified and asked to
explain the discrepancy.
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