Corrections to Lecture Notes

Corrections are shown in the order they were reported. Please let me know if you find an error that is not listed below.

Corrections to Lecture Notes

• Lecture 3: Sequential Logic Design

  To infer a D flip-flop instead of a latch, Design Compiler requires that the process for the D flip-flop be written as follows:

   process(clk)
   begin
      if clk'event and clk = '1' then
         q <= d ;
      end if ;
   end process ;
  

  The clk'event tells DC that the memory element is edge-triggered rather than level sensitive.

  Similarly the process that generates the sequential logic for the state machine should read:

      -- sequential logic
      process(clk)
      begin
         if clk'event and clk = '1' then
            current <= nexts ;
         end if ;
      end process ;
  

• Programmable Logic Devices, page 2, column 2: The part number is 22V10, not 20V10. The 22 refers to [half of] the number of inputs to each AND gate (vertical lines, in this case 11 inputs pins, 1 clock pin and feedbacks from the 10 outputs) and the 10 is the number of outputs (OR gates).
• Combinational Logic Design, page 4, column 1: The syntax in the lecture notes for vector ranges with increasing subscript values is wrong. The syntax is (1 to N), not (1 upto N).
• 8088 Processor Bus, page 2, column 2: ``IO/M* should be HIGH for an I/O read or write.''
• The lecture titled "IBM PC Interrupt Structure and 8259 DMA Controllers" should have been titled "IBM PC Interrupt Structure and 8259 Interrupt Controller".

Corrections to Assignment Solutions

• Assignment 4: Timing Analysis
  • The expression for the guaranteed value of T_ACCE should be t_GLQV (not t_ELQV).
  • The expressions for t_AH and t_CH (address and chip select hold times) are incorrect. The 16550 address lines are driven from the latch, not directly from the address bus so t_LLAX does not apply (t_LLAX is the guaranteed hold time for the latch). The chip select decoder is driven from bits 8 to 15 of the address bus. Unlike the LS 8 bits of the address bus, these bits are not multiplexed and stay valid until T4.

    This means that the 16550's address inputs will be valid until the next bus cycle and the chip select will be valid until T4. Both requirements are met by a large margin:

    The guaranteed hold time for the 16550 address input will be the time from the falling edge of ALE to the rising edge of ALE in the next bus cycle: 4t_CLCL - (t_CHCL-t_CHLL(max)) - t_CLLH(min) = 800 - ( 66 - 85 ) - 0 = 819 ns.

    The guaranteed hold time for the 16550 chip select input will be the time from the falling edge of ALE to when A8 to A15 becomes invalid at the end of T4: 3tCLCL + tCHLL(max) + tCHDX(min) = 600 + 85 + 10 = 695 ns.