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One student asked:

> What happens if the CS* goes inactive during one of the wait states.
>
> Will the processor continue to generate wait states until the 3 clock
> cycles are complete or will it return back to initial state?
>
> For now, it seems to make more sense if it returns back to initial state,
> I think I will implement as such. . .

The question stated:

        Your design should generate DTACK* three clock cycles
        after CS* goes active.  DTACK* should go false at the
        clock edge where CS* goes inactive.

You're right, the question is ambiguous with respect to what
happens when CS* goes inactive in one of the wait states.  You
can implement your solution in either fashion.

In an actual system CS* would be active until DTACK* is asserted
so either behaviour would work properly.

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another student asked:

> hi there, this has to do with assignment 4.  For question 3 what does the
> reset line do.  There is nothing in the paragraph above, that describes
> the circuit we are to build, about a reset line.  thanks.

DTACK* should go inactive when RESET* is asserted.

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and then:

> I see, is this the same reset that is in question 2.  Because you never
> mention reset in question 3 untill you talk about the test vectors.

The second point in the introduction to the assignment asks for a
RESET* active-low input for each sequential circuit.

> i also have another question about #2, what is supose to happen when
> there is no longer a clock signal.  Can we just say that the state that
> the PAL was in before the clock signal died will be the current state.
> ie you can no longer change states?

If the clock stops the processor will stop also and wait states
would be irrelevant.  You don't have to worry about the clock
stopping.

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and for some reason I replied again:

> I see, is this the same reset that is in question 2.  Because you never
> mention reset in question 3 untill you talk about the test vectors.

The source of the RESET* signal is not part of the device's
specification.

But yes, these chips are typically reset by a common reset
signal.  This signal is normally tied to a pull-up resistor and
is pulled low by some circuitry that ensures a minimum reset
pulse duration.  This signal is used to reset the CPU, I/O chips
and things like this two-state address decoder.

> i also have another question about #2, what is supose to happen when
> there is no longer a clock signal.  Can we just say that the state that
> the PAL was in before the clock signal died will be the current state.
> ie you can no longer change states?

Yes.  If there is no clock a sequential device will not change
states.

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-- 
Ed Casas (edc@ece.ubc.ca)

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