EECE 379 : Digital and Microcomputer System Design

Instructor

Lectures and Tutorials

Labs

Lab Schedule

To switch lab sections: (1) Find someone willing to change into the section you are currently registered for (you can use the course mailing lists for this), and (2) both persons must notify the lab TAs by e-mail. Since there are (almost) no free lab spaces available you must show up for your scheduled lab period.

The lab sections are scheduled as follows:

        Lab 1         Lab 2         Lab 3         Lab 4     
	                               	                  
Mon  Sep 18 - D    Oct 16 - D    Oct 30 - D    Nov 20 - C
Tue  Sep 19 - A    Oct 17 - A    Oct 31 - A    Nov 21 - B  
Mon  Sep 25 - C    Oct 23 - C    Nov  6 - C    Nov 27 - D  
Tue  Sep 26 - B    Oct 24 - B    Nov  7 - B    Nov 28 - A  

Open Labs

Lab Procedure

For most labs you will not have enough time to design, build and debug your circuit during the lab. Therefore, you must design and verify your solution (through simulation) before coming to the lab. You will be required to hand in the source code and correct simulation results before starting the lab.

You must print out the revised source code (VHDL and/or assembler) and demonstrate your working design to the TA before the end of the lab session. The TA will then ask one or two questions about your program to make sure you understand the material. If did your own work you shouldn't have any problems answering the question(s).

A short lab report must be handed in to the course assignment box (see below) before the start of your next lab on the dates shown above. This report should include a brief description of your design, source code listings, schematics or block diagrams, and answers to any questions posed in the lab notes. Lab reports should be placed in the box marked "EECE 379 Assignments" outside MCLD 332.

Lab Marking

	complete, simulated and correct pre-lab		1
	a program and/or circuit that works properly	3
	correct answers to questions after demo		1
	accurate, complete and well-written report	1 

Note: If a working circuit is not demonstrated by the end of the scheduled lab session you will receive a mark of zero for the second component (0/3). If you do not complete the lab on time hand in a report describing your simulated circuit. If the report is not handed in on time you will receive zero for the report (0/1).

You must complete all four labs to pass the course. All four lab marks will count towards your final mark.

Plagiarism

Assignments

Assignments are to be done individually. Students are encouraged to seek help from classmates but copying is not allowed. Possible penalties for plagiarism include a mark of zero for all assignments.

Bonus marks may be awarded for the fastest, the smallest and the most readable (as judged by the TA) designs submitted for each assignment.

Teaching Assistants

Web Page

The lecture notes, assignments, labs and solutions will be available from the Web page in PDF and other formats. Free software to view and print PDF documents (Ghostview, xpdf, Adobe Acrobat Reader) is available for most computers.

Mailing List

Students should post questions or answers about the course material to the eece379 mailing list.

Instructions on subscribing are available on the course Web page.

The mailing lists can also be accessed through the eece379-announce and eece379 archives.

Text

Detailed notes will be distributed before the relevant lecture. The notes will often contain exercises or sections to be completed during the lecture.

Please wait until the end of the lecture before taking extra copies. You can always print copies from the course's Web page (see below).

Other References

• Contemporary Logic Design by Katz, Addison Wesley, 1993. Is the EECE 259 textbook and covers some of the material on logic design. If you already have that textbook you may wish to refer to it for alternative explanations of various topics.
• VHDL for Logic Synthesis: An Introductory Guide for Achieving Design Requirements, Second Edition, by Andrew Rushton (McGraw-Hill, 1998, $98) is a concise guide to logic synthesis using VHDL.
• VHDL Made Easy by David Pellerin and Douglas Taylor (Prentice-Hall, 1997), $91, is an easy-to-read introduction to using VHDL for design.
• The Designer's Guide to VHDL by Peter J Ashenden (Morgan Kaufmann, 1996) is an complete reference on the VHDL language.
• The 80x86 Family by John Uffenbeck (Prentice-Hall, 1998) covers the 80x86 family of microprocessors and their support chips in detail.
• The Indispensable PC Hardware Book, third edition, by Hans-Peter Messmer (Addison-Wesley, 1997), $59, is a detailed reference on the IBM PC Architecture.
• The Art of Electronics, second edition, by Paul Horowitz and Winfield Hill, Cambridge University Press, 1989, $100, is a good practical reference book on most aspects of electronics although much of the material is now dated.

Evaluation

	final exam  		49%
	midterm exam 		20%
	assignments 		10%
	labs			20%
	participation		 1%

The participation mark will be awarded (at the end of the course) to students that asked or answered a non-trivial question on the course mailing list. Please include an approximation of your real name (but not your student number) when posting to the mailing list.

Changes to the marking scheme will require the agreement of the instructor and all of the students.

Software

A free 80x86 assembler is available on the course Web page and on the department's PCs.

Intended Audience

EECE 379 is designed for students in the Electrical Engineering rather than the Computer Engineering stream. The course covers the same material as a combination of EECE 353 (logic design) and EECE 465 (microcomputer design) but does not cover the material in as much depth.

If you are in the computer engineering option you should probably take EECE 353 plus EECE 465 rather than this course. Ask your faculty advisor for more details.

Prerequisites

Objectives

• design and test combinational and sequential logic circuits using the synthesis subset of VHDL covered in the course
• give the values of the 80386 data, address and control bus signals during read or write cycles to I/O or memory
• describe the steps carried out by an 8088 processor in response to an interrupt
• select the appropriate type of memory device for a given application (SRAM, ROM, DRAM, flash EEPROM, etc)
• draw schematics of multi-chip memories for a given memory chip, data bus width and address range
• compute margins for read and write cycles using CPU and memory data sheet timing diagrams and specifications
• select and justify the choice of I/O strategy (polling or interrupt-driven; programmed I/O or DMA) for a given application
• write software to control programmable peripherals (e.g. DMA controllers, interrupt controller, timer/counter, parallel and serial interfaces) in 80x86 assembly language by reading and writing status, control, and data registers
• describe and analyze the behaviour of ``RS-232'' and SCSI bus signals during common operations

Course Outline

• review of digital logic design
• logic synthesis with VHDL
• the 80386 microprocessor
• memory system design
• polled, interrupt-driven and DMA interfaces
• system buses (ISA, PCI)
• peripheral buses (Serial, Centronics, SCSI)

Related Courses

• CPU design is covered in EECE 476.
• IC design is covered in EECE 479.
• operating systems are covered in CPSC 415 or ELEC 494.