Marking of Assignment 3
Question 1 was marked in two parts and counts as two assignments.
Each part was marked out of 10. Marks were assigned as follows:
Part 1
- 1 for the VHDL code of a package defining
the addrress and word types
- 1 for the memory VHDL code
- 2 for memory simulation output showing that the three
memory writes and reads are done correctly
- 1 for the ALU VHDL code
- 2 for ALU simulation showing correct execution of hold, load, add
and subtract operations
- 1 for the I datapath VHDL code
- 2 for the I datapath simulation showing correct operation of
hold and load
Part 2
- 1 for PC VHDL code
- 2 for PC simulation results showing correct results for
the possible operations (hold, increment, jump and reset)
- 1 for the instruction decoder VHDL code
- 2 for the decoder simulation results for each instruction,
including jump/no jump results for each conditional
jump (total of 9 tests)
- 1 for top-level VHDL code
- 3 for final simulation results showing correct execution
of the test program
including conditional and infinite loops
For full marks the VHDL code should be correct, reasonably clear
and include some comments. For full marks the simulation results
should cover all of the test conditions specified in the
assignment and generate the correct results.
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