Questions and Answers

> I was studying the 80386sx and I do not understand how the BLE*
> and BHE* are asserted.
> 
> In my notes I have that if Ao = 1 then BHE* = 0 and if A0 = 0
> then BHE* = 1.  But I think that sometimes they can both be
> equal to zero.  Please help me understand how they are
> asserted.

Since the 386sx has a 16-bit data bus it can read/write two bytes
in a single read/write cycle.  In that case both BHE* and BLE*
are asserted simultaneously.



> 1)  For memory design, what is the 'byte-select' bit used in the
> byte-select address line?  How do we 'find' it?

When a memory is more that 1 byte wide then as many of the least
significant bits as are required to uniquely select one of the
bytes in each word are what I call the "byte-select" bits.  For
example, if the memory were 4 bytes wide then the LS 2 bits (A0
and A1) are byte selects, if the memory is 8 byte wide then A0
through A2 are byte selects, etc.

> 2) How many questions are on the Exam, and what is the format?
> Is it similar to the midterm?

The questions will be be similar to the midterm and assignment
questions (VHDL design, timing analysis, memory design, etc) as
well as multiple-choice and/or short-answer questions.



> I'm doing assignment #5 and am reading the data sheets from NEC.  They
> have 2 tables for specifying both the read and write cycles timing
> requirements.  I'm wondering which one I should be using?  Thanks.

I should have specified Vcc (supply voltage).  You can assume Vcc
is 5 volts (use Tables 1/2, the fastest values).



> I am doing problem 2 of this assignment.  The code I wrote is
> synthesized with no error.  But as i look at the schematic of
> the resulting circuit, I find some square blocks.  I am not
> sure whether they are flip flops or not.  Could you please
> explain?

It sounds like you are using the wrong library.  Check to make
sure you have copied the .synopsys_dc.setup into your working
directory (see the Web page for more details).



> I am having some difficulties completing the assignment.  The
> first question says that the CPU address bus has 24 bits while
> I calculated that each device (4 of them) needs only 14 bits.
> How can this be implemented, do I only need to use a selected
> number of the address bits or do I use an address decoder?

The questions says you need to use an address decoder.  The
principle is the same as we covered in class, only you will have
more bits going to the decoder.  Unfortunately, we didn't have
time to cover the design of decoders in detail on Friday
(although this only affects Questions 2 and 4).

> My second question is on question 2, it says that the signal a
> is the address inputs and e are the enables for the selected
> banks.  I do not understand what has to be done in this
> question.  I know that the memory bank responds to addresses of
> the form 111111111... or 000000001...  What exactly does the e
> signal mean.

The bits of the vector `e' are the enables for the different
banks.

> Also, would really appreciate it if we could get an extension
> until wednesday.  I have not been able to come down to UBC to
> implement the VHDL programs because of time constraints.  Also,
> I am having trouble understanding some of the concepts behind
> memory systems and I need more time to get a good handle on
> these concepts.

We will discuss the possibility of an extension on Monday morning
(I will suggest extending it by 1 day so you can get the
solutions on Wednesday).

However, both VHDL designs are very simple (the architectures
only require 2 and 4 lines respectively) and do not have to be
simulated.  Once you understand the principles I doubt it would
take you more than 1/2 hour to do the VHDL part.



> > I've implemented a device with VHDL but the synthesized
> > output is comprised of blocks rather than combinational
> > logic.  Can you explain what does that mean?

You probably need to create a .synopsy_dc.setup file in your
working directory to define the target technology.  If you want
to target a more realistic device technology (Xilinx FPGAs) you
can try using the instructions given in:

	http://www.ece.ubc.ca/~edc/464/xilinx.html

> > 	I've also spotted the compiler says that any delay used will not
> > be synthesized.  Why?
...
> architecture rtl of sound_sync is
> begin
>   process(sync)
>   begin
>     if sync = '1' then
>       drive <= '1';
>       drive <= '0' after 250 ms;
>       sync <= 'Z';
>     end if;
>   end process;
> end rtl;

The VHDL statements for generating delays are meant for
simulation and modelling.  To synthesize delays you have to use
clocks and counters.  

If your inputs aren't synchronized to a clock then you will end
up with some timing error (``jitter'').  For example, to get a
250 ms delay with a maximum of 1 ms `jitter' you could use a 1
kHz clock and an 8-bit counter.  You would set the output high
and start the counter when you detected the sync pulse and reset
the output and stop the counter when the count reached 249.



> I have another question, do I need to type
> library ieee;
> use.ieee...
> ...
> 
> for each entity even if i'm putting everything in one file?  Or
> is it okay to just have these directives once at the beginning
> of the file?

Yes, you need to put these before every ``design unit.''

> Also, can I declare a user-def type locallly within the
> architecture, and not as a package?
> Right now, I have 
> 
> architecture rtl of ---
> 	signal ....
> 	signal ...
> 	type ....
> begin
> ...
> end rtl;

Yes.



> I was wondering if you could help me understand this message
> from the compiler.  It keeps complaining that "UNSIGNED is not
> declared." What does that mean?  It refers to my variable
> declarations in the entity.

It probably means that you have not put the line:

	use ieee.std_logic_arith.all ;

in your file.



> When synthesizing my design I get a warning for the code:
> 
> for all: datapath use entity work.datapath (rtl);

You can ignore this warning.




> My assignment 3 is basically syntax error free but the read -f statement
> doesnt like the following two lines
> 
> ra <= ra srl 1;
> rb <= rb sll 1;
> 
> ra and rb are the a and b registers of unsigned type and they are 16 and
> 31 bits wide respectively.  
> 
> I am trying to shift them. I came across an example for using sll in VHDL
> cook book on Elec 353 web pages.  It looks like
> 
> a := x sll 2; for a left shift but that syntax doesn't work either.

The sll and slr operators are part of a more recent version of
VHDL called VHDL 93.  The Synopsys tools don't understand these
extensions.  Use slices and concatenation as described in the
lecture notes instead.



> Could you please answer the questions regarding the second
> assignment?  Do SR, S1, S0 have values like Undefined, Z (high
> impedance)?

In the testbench only the values high and low are applied to
inputs.  Real-world logic only recognizes these two values.

> If the synchronous reset is active low, does that mean a LOW in the
> truth table is actually HIGH for the reset?

Active-low means the signal is TRUE when it's low.  In this case
the device should be reset when the input is low.  The exact
behaviour is described in the truth table for the device.



> I'm doing the assignment 2 right now and I've found that the
> compiler cannot find the std_logic_1164.all because it's not in
> the WORK directory. . I notice that it's not in the ~elec379
> directory either.
>
> May I know where I can copy that file from.  Thanks.

The WORK library (in the ./WORK directory) only contains files
created by you.  The package std_logic_1164 is in the IEEE
library.  On our system it is in the

	/usr/applic/synopsys/packages/IEEE/lib 

directory (although you don't need to know this).

Use the following two statements before each design unit to
make everything in the std_logic_1164 package available:

	library ieee ;
	use ieee.std_logic_1164.all ;



> What is the difference between a system bus and a peripheral
> bus since a system bus also connects to peripherals?

The system bus is not normally connected directly to peripherals.
There usually has to be some sort of intermediate interface
containing at least data and status registers and, for high-speed
peripherals, often more extensive logic to implement data
buffers, interrupt control and sometimes DMA functions.



> Can a peripheral bus have an address bus?

Some peripheral buses, like SCSI, IEEE 488 (HPIB/GPIB) or USB,
allow multiple devices to "sit" on the same peripheral bus.  In
this case there is an addressing function but it is nearly always
multiplexed over the common address/data bus.  We will talk about
how this is done later on in the course.