Synthesizing Hierarchical Designs

Complex designs will involve a hierarchy of entities ("design units"). The following instructions describe how to use dc_shell to synthesize a hierarchical design. You must set up your environment (the .cshrc.login file, the .synopsys_dc.setup file, and the WORK directory) as described previously.

In a large design the design units may be spread among various files. For example, if the parity generator example in the lecture notes had been split into the files xor2.vhd and parity.vhd then the files would be read using the commands:

	read -f vhdl xor2.vhd
	read -f vhdl parity.vhd

The name of the top-level design unit to be compiled is set using the command:

	current_design parity

where parity is the name of the top-level VHDL entity. The parity generator uses three instances of the xor2 design unit. To avoid duplicate names you must create uniquely-named copies using the command:

	uniquify

To synthesize the design use the command:

	compile

To create schematics of all of the design units (four, in this case) use the command:

	create_schematic -hierarchy

To print all of the schematics use the command:

	plot -hierarchy

To create or plot a schematic only for the current design unit you can use the create_schematic and plot commands without the -hierarchy option.

If you are using an X display and want to preview a schematic before printing it, use the command:

	plot -output parity.ps -hierarchy

and the UNIX (not dc_shell) command:

	gs parity.ps

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