Checking Timing Requirements with Max+PlusII

You should verify that your designs will operate at the required clock frequency. Use the following procedure:

Select File -> Project and set the project name as usual.
Select the menu item Max+PlusII -> Compiler.
Make sure the Processing -> Timing SNF Extraction option is enabled.
Compile your project.
Select menu item Max+PlusII -> Timing Analyzer.
Select Analysis -> Registered Performance to bring up a dialog box.
Click on Start.
Check that your synthesized design's maximum clock frequency is sufficiently high.
If not:
- Select Max+PlusII -> Compiler.
- Select Assign -> Global Project Logic Synthesis to bring up a dialog box.
- Select "FAST" in the Synthesis Style box and move the "Optimize" slider towards the "Speed" side.
- Re-compile your code and check the maximum speed again.

If your design won't run at the required clock frequency try reducing the number of levels of combinational logic in your design (e.g. use selected rather than conditional assignments). If it still doesn't work fast enough then e-mail me (edc@ece.ubc.ca) a copy of your code and I'll make additional suggestions.

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