Marking of Assignment 1

Only Question 1 was marked. Marks were assigned as follows:

• 1 for correct entity name (using your own initials)
• 2 for a VHDL description that looks like a plausible solution to the problem
• 1 for including comments in the VHDL code (something more than just your name)
• 2 for using processes according to the course requirements: each process must include one and only one if statement and the condition in the if statement may only be of the form "clk'event and clk='1'"
• 1 for including a diagram
• 1 if the diagram structure matches your VHDL code in structure
• 1 if the diagram is complete (all signal names and bus widths)
• for each of the three test cases:
  • 1 mark for the correct test input (clk and buttons)
  • 2 marks for the correct response (lock opens only in second test case)