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> Another Question is supposed the RAM, ROM, PC Datapath and A > Datapath are create as individual package where Controller can > called. Does VHDL view each individual package as a program or > it will treat everything as one program. The VHDL compiler can analyze ("compile") each entity separately. In order to synthesize a netlist or simulate the behaviour ("elaboration") of the top-level entity the VHDL synthesizer will analyzer your top-level entity and combine it with any required components. These components will typically come from a package. For this assignment you should synthesize and test each entity (except the top-level one) separately, then put them all into a package as components, and then use that package in your top-level design. > If the formal is true, will VHDL keep track of those signals > that are declare in each package? (which means if the > controller called PC datapath, there will be a PC counter > signal used. if Controller called PC datapath again, will this > signal be redeclared (or reinitialised) or will it retain the > old value.) Hmmm. If you are asking whether the names of the port signals need to be the same in the entity declaration, the component declaration and the component instantiation then the answer is no. > If the latter is true, is there are two signals of the same > name in two different package, will VHDL be smart enough to > identify it and not overwrite any of them? In the examples we have seen in class the mapping of signals between the component declaration and the component instantiation is by position only, not by name -- it works the same as a function call in a programming language.
> I don't know the syntax for the conv_integer(), > conv_unsigned(), unsigned() and std_logic_vector() conversion > functions. In fact, I don't know what these functions actually > do. Get a copy of the VHDL and 1164 reference sheets available on the course home page. Or use the MaxPlusII on-line documentation (use the "Index" button).
> I just wonder what should be handed in on this Friday? Are we > just handing in the code? No. You must hand in the simulation results as specified in the assignment as well. > What about if I want to change the code next week (if the > current code doesn't work)? Do I need to simulate anything? If it simulates properly, it will probably work properly in your final design. You can change what you hand in next week if necessary.
> I am not sure what the A datapath and Controller do. Are all > those opcodes (LOAD, STORE, LOADI, etc..) supposed to be > implemented in the A datapath or in the Controller? Because, > it is under the "Instruction Decoder" section in the assignment > where all the opcodes are described. Also, it is said, under > the same section, "Design the controller so that the CPU can > execute the following instructions". Does this mean they are > to be implemented in the Controller? If they were to be > implemented in the A datapath, why do only "add", "and" & "not" > appear in the diagram and the other operation not? The CPU's 8 instructions are implemented in the controller. The datapaths implement other, simpler, instructions as specified in their descriptions. > By looking at the diagram for A datapath, it seems like it does > "something" to the data from the data RAM depending on the > opcode provided, and puts it back to the data RAM. But, I > don't know why it needs "the address field of current > instruction" input? Look at the definition of the LOADI instruction. > Opcode and address field are stored together in the ROM as an > instruction, so why would they need to be input separately into > the A datapath? The instruction address field comes from the current instruction, the A datapath opcode comes from the controller. > and how can they be separated? Use subscripts (e.g. "rom_out(5 downto 0)"). > Why is LOAD opcode not used in the program but still needed? This is supposed to be a general-purpose CPU. Any given program may not use all instructions.
> I was going to ask this on the newsgroup but I could not figure > how newsgroup works. I'll try to set up an alternative interface soon. > Anyways, my problem is that I cannot get MaxPlus2 to complie my > codes for assignment #3, it says that data_types (my package > file) does not contain a architecture body. If I can't get my > data_types.vhd to compile, then I can't use the work files in > other .vhd codes. This warning is the expected behaviour. After you "analyze" the package it will be available to other design units. > When I compile the code, do I give different project name for > different code?? For examples, project name ram for ram.vhd, > project name rom for rom.vhd and so on. Yes. Use a different project name for each entity and compile/test each one separately. To combine the different components into the final design you must write another file/entity/project that instantiates the different components and connects them up.
> I don't quite understand how the ROM works. It takes five bits > from the current PC and change them to current instruction, > which is 8 bits wide. I know the MS three bits are the op code > and the rest is the address field. That's correct - the MS 3 bits of the instruction are the opcode of the instruction and the LS 5 bits of the instruction are the address field of the instruction. > However, I just don't understand how to get the op-code to > export the 8 bits wide PC instruction. I don't understand what you mean by "export". The ROM stores 32 instructions at ROM (instruction memory) addresses from 0 to 31. As you've explained above, the ROM is a lookup table that converts the value of the PC on its input (5 bits) to the current instruction on its output (8 bits).
> I can't figure out how to start a new line using interupt > 21H. Could you give me a hint? Printing character 13 doesn't > seem to work. You have to print both a 13 (carriage return - move the print head to the left margin) and a 10 (line feed - move the paper up one line).
> I have a few questions about memory storage conventions for the 8086 > architecture. > > 1) At each vector locations, which is stored first: the CS or the IP > information? IP. See the Web page for other hints. > 2) When I load a 16-bit value from memory to the processor, does the > value appear in the processor in little-endian form? No. Little-endian only refers to the way multi-byte values are stored in (byte-addressable) memory. > 3) How do I use interrupt 21H to print a character? Let AH=02H and let > AL=the character in ASCII? Use DL for the character. See the example at the end of lecture 6. > Questions about my own computer: > > 1) If I am running a MAC, can I still simulate 8086 assembly > language? Yes, there are 8088/DOS emulators for Macs but I don't know the details -- maybe a Mac expert can tell you. I think 80386/Windows emulators would be too slow to run the MaxPlusII software. > You seem to have assumed that everybody in the class has access > to a PC that runs DOS. I make sure that all of the assignments and labs can be done either on the PCs in the basement or on the Sun Workstations. You should have (or should get) accounts on both of these systems. The assembler executable is small enough that you can download and store a copy into your own directory. I agree that using the machines at school is not as convenient as having your own machine at home, but I don't see any solution to this problem. I understand your frustration since don't use DOS or windows myself. > 2) If my software doesn't support PPP, how do I obtain > infomation about 8086 machine language instructions and DOS > interrupts? You seem to have assumed that everybody in the > class has graphical WWW access. Thanks for pointing this out. I try to make everything on the course web page accessible to text-mode browsers. For example, all of the lecture notes can be downloaded in various printer and graphics formats. But I forgot about this when making the link to the interrupt list. The original interrupt list was a flat text file and I should have included a link to that version as well. You won't need it to do the assignment since the two interrupts you need to use are included in the examples in the lecture notes. I *do* assume that you can display PDF files. But PDF file browsers/printers (either Acroread or Ghostscript) are available for almost all computers, including the ones in the EE building.
> I am working on the assignment 2 and nearly done. However, I > just can't get the "hex" values printed. I know the print > function in the notes prints the ASCII values of the byte. > However, we are trying to print the hex values instead of its > ASCII equivalent. I just wonder where I can find information > on this? I don't know if I should change the hex to ASCII or > just that there is a way to print hex. First, expressing a number in a different base does not change its value. To make a character of the desired shape appear on the screen, you have to provide DOS (or any other print routine) with the ASCII code for that character. An ASCII table will show you the ASCII code for each character. This ASCII code is a number (you can express it in any base you want). Your "print a hex digit" function needs to convert a four-bit number (0-15) into the ASCII value for the appropriate character, i.e: 0 -> 30H 1 -> 31H ... 9 -> 39H 10 -> 41H ... 15 -> 46H
> I have a question about assignment #1. In the handout, it says one of > the items we have to hand in is a waveform simulation showing that the > counter will "count through all legal values and wrap back to 5." I > have checked the specs for the 162A, and it doesn't appear (maybe I > missed it) that this is part of the description. It would seem that > even if the number 5 was loaded using the PE* pin, the counter would go > from 9->0 instead of 9->5 (the PE* pin must be de-asserted for the > counter to count). Could you help clarify this please? Thanks. The counter should count from 5 to 9, wrap to 0 and count back up to 5. Unless you observe it going from 5 around to 5 you won't have checked all of the ``legal'' state transitions. The spec sheet includes a state transition diagram that specifies this part of the behaviour.