ELEC 379 : Digital and Microcomputer System Design

Instructor

Office Hours

Lectures

Tutorials

Labs

The tentative lab schedule is as follows:

Lab   Topic                                Starts (L1A) Report Due

 1    Address Decoder                      Sep 22       Oct  6
 2    Wait State Generator                 Oct  6       Oct 20
 3    Parallel Output Port                 Oct 20       Nov  3 
 4    Serial Output Port                   Nov  3       Nov 17
 5    to be decided                        Nov 17       Dec  1 

Except in case of equipment shortages all labs are to be done individually.

All labs will require that you design and simulate a circuit before the lab. You will be required to hand in the source code for your design before starting the lab.

You must print out the source code and demonstrate your working design to the TA before the end of the lab session. The TA will then ask you one or two questions about your program to make sure you understand the material. If did your own work you shouldn't have any problems answering the question(s).

A short lab report must be handed in to the course assignment box (see below) before 9:30 AM on the due dates shown above. This report should include a brief description of your design, source code listings and schematics, and answers to any questions posed in the lab notes. Lab reports should be placed in the box marked "ELEC 379 Assignments" outside MCLD 332.

Each lab will be marked out of 5 as follows:

	correct program/circuit		3
	answers after demo		1
	accurate/complete/neat report	1 

If a lab is not demonstrated on time you will receive a mark of zero for that lab (0/5). If the report is not handed in on time you will receive zero for the report (0/1).

You must complete all labs to pass the course -- even if you would get a mark of zero for a lab.

Each student must submit an original solution. Possible penalties for plagiarism include a mark of zero for all labs.

Assignments

Assignments are to be done individually. Students are encouraged to seek help from classmates but copying is not allowed. Possible penalties for plagiarism include a mark of zero for all assignments.

Teaching Assistants

Web Page

The lecture notes, assignments, labs and solutions will be available from the Web page in PDF format. Free software to view and print PDF documents (Ghostview, Adobe Acrobat) is available for most computers.

Text

Detailed notes will be distributed before the relevant lecture. The notes will often contain exercises or sections to be completed during the lecture.

Please wait until the end of the lecture before taking extra copies. You can always print copies from the course's Web page (see below).

Other References

VHDL for Logic Synthesis: An Introductory Guide for Achieving Design Requirements by Andrew Rushton (McGraw-Hill, 1996, US$55) is a good text on logic synthesis using VHDL. VHDL Made Easy by David Pellerin and Douglas Taylor (Prentice-Hall, 1997) is an easy-to-read introduction to using VHDL for design. The Designer's Guide to VHDL by Peter J Ashenden (Morgan Kaufmann, 1996) is an complete reference on the VHDL language. The 80x86 Family by John Uffenbeck (Prentice-Hall, 1998) covers the 80x86 family of microprocessors and their support chips in detail. These books cover much more than you will need for this course. A number of tutorials and a short book on VHDL are available on the net (see the Web page).

The Art of Electronics, second edition, by Paul Horowitz and Winfield Hill, Cambridge University Press, 1989, is a good practical reference book on most aspects of electronics although much of the material is now dated.

Evaluation

	final exam  		50%
	midterm exam 		25%
	assignments 		10%
	labs			15%

Newsgroup

Intended Audience

ELEC 379 is designed for students in the Electrical Engineering rather than the Computer Engineering stream. The course covers the same material as a combination of ELEC 353 (logic design) and ELEC 465 (microcomputer design) but does not cover the material in as much depth.

If you are in the computer engineering option you should probably take ELEC 353 plus ELEC 465 rather than this course. Ask your faculty advisor for more details.

Prerequisites

Objectives

• design simple combinational and sequential circuits using the synthesis subset of VHDL covered in the course
• describe the response of a circuit described in VHDL to a given input
• describe the 80386 processor bus and the behaviour of its signals during read and write cycles
• describe the response of an 80386 processor to an interrupt
• compute timing margins for read and write cycles from CPU and memory timing specifications
• design multi-chip memory banks that meet bus loading and timing requirements using common memory ICs (SRAM, DRAM, EPROM)
• select and justify the choice of I/O strategy (polled, interrupt, or DMA) for a given application
• write software to control programmable peripheral chips (e.g. DMA, interrupt controller, timer/counter, parallel and serial interfaces) in 80x86 assembly language
• describe and analyze the behaviour of SCSI and RS-232 bus signals during common operations

Course Outline

• review of digital logic design
• logic synthesis with VHDL
• the 80386 microprocessor
• memory system design
• polled, interrupt-driven and DMA interfaces
• system buses (ISA, PCI)
• peripheral buses (Serial, Centronics, SCSI)