| Name | Last modified | Size | Description | |
|---|---|---|---|---|
| Parent Directory | - | |||
| asg1.pdf | 1998-09-25 09:43 | 24K | VHDL Synthesis | |
| asg2.pdf | 1998-10-07 09:45 | 21K | Assembly Language | |
| asg3.pdf | 1998-10-15 14:57 | 10K | RTL Computer Design | |
| asg3a.pdf | 1998-10-15 14:57 | 40K | Hints for Assignment 3 | |
| asg4.pdf | 1998-10-30 13:46 | 6.1K | PC ISRs | |
| asg5.pdf | 1998-11-12 22:20 | 8.5K | Timing Analysis | |
| asg6.pdf | 1998-11-25 18:44 | 5.3K | Serial Interfaces/Metastability | |
| sol1.pdf | 1998-10-07 20:25 | 30K | Assignment 1 Solutions | |
| sol2.pdf | 1998-10-18 21:44 | 32K | Assignment 2 Solutions | |
| sol3.pdf | 1998-10-29 13:53 | 27K | Assignment 3 Solutions | |
| sol4.pdf | 1998-11-12 10:20 | 16K | Assignment 4 Solutions | |
| sol5.pdf | 1998-11-30 13:49 | 13K | Assignment 5 Solutions | |