Marking Scheme
- Only the items below were checked.
- One mark was assigned for each item unless otherwise indicated.
Labs
Note: For any solution to be considered correct the course coding
guidelines must be followed. No marks awarded otherwise (e.g. use of
if/else, begin/end or case statements).
Lab 0: (12)
Report formatting (2)
- has cover page with (1) course name & number, (2) lab number &
title; (3) student name & number; (4) date (-1 per missing item)
Code Listing (3)
- includes required file-level comments
- monospaced font with single spacing
- indentation matches code structure and indentation levels are consistent
- text, not an image (-1)
Screen capture (1)
- includes readable compilation report details
- shows more than compilation report (e.g. complete screen) (-1)
- not taken with a screen capture utility (e.g a phone) (-1)
Block diagram (3)
- legible, upright
- drawn by student, not Quartus RTL Netlist Viewer
- matches diagram in Report and Video guidelines in all respects
(symbols, port labels, bus widths, expressions)
Submitted video file (3)
- shows the blinking LED
- properly oriented
- less than 25 MBytes and plays in browser
- a file, not a link (-3)
Typical Comments:
1 screen capture of code: -1
2 incorrect indentation: -1
3 not necessary
4 excessive indentation: -1
5 no lab title: -1
Lab 1 (10)
- pre-lab (1)
- cover page (1)
- block diagram matching code (1)
- listing matching demo (1)
- compilation listing matching your code (1)
- demo (video or in lab) (5)
- marks deducted for any report and video guidelines not followed
- no marks if video is too large or not viewable in browser
Typical Comments
1 missing en and row outputs: -0.5
2 missing values: -0.25
3 crop to show only the compilation report.
4 use an expression here: -0.25
5 not needed
Lab 2 (10)
- pre-lab done (1)
- listing conforming to coding guidelines (2)
- monospaced font, single-spaced listing: -1
- file-level comments -1
- consistent indentation -1
- use of always_ff with single non-blocking assignment -1
- block diagram matching the Verilog and conforming to report
guidelines (not from Quartus) (1)
- correct digits displayed in the right digit position (2, -1 for each incorrect digit)
- correct digits displayed in the right time order (2, -1 for each digit in wrong order)
- all digits displayed simultaneously with 5 kHz clock (1)
- correct orientation of digits on video (1)
Typical Comments:
1 Pre-Lab OK
5 demo OK
2 No pre-lab: -1
3 missing segment logic (assign): -1
4 missing file-level comments: -1
Lab 3 (10)
- both demos completed during the lab: 10
Lab 4 (10)
- block diagram matching the student's keypad.sv conforming to report
guidelines (1)
- one multiplexer per conditional operator
- one register per always_ff statement
(not generated by Quartus, not the one from the lab instructions,
not using arbitrary symbols)
- Verilog listing with (2)
- correct file-level comments
- correct indentation
- screen capture of compilation report (1)
- demo or video showing effect of pressing each key (6)
- -1 for each key displaying incorrect value (except * and #)
- -3 for each incorrect display for * or #
Lab 5 (10)
- pre-lab: a module and .csv file ("good-faith" attempt, not necessarily correct) (1)
- listing of DUT .sv file (1)
- -0.5 per coding or report guidelines violation
- -0.5 if a design requirement not met (e.g. no module instantiation)
- listing of testbench .sv file (1)
- -0.5 per coding or report guidelines violation
- screen capture of simulation waveforms (1)
- screen capture of testbench transcript (1)
- correct results (5):
- reset asserted and sets output to zero
- sequence of 8 input digits corresponds to the student's ID
- count output values increase by correct amounts
- correct final value
- correct error message on last test vector
Lab 6 (10)
- pre-lab (answers to 1 and 4 correct and attempted others): 1
- one mark per screen capture (4)
- showing a 3.3V square wave on TP1
- showing a 5V square wave on TP3
- showing TP3 at 5 V and inverted relative to TP2
- showing TP3 at 3.3 [inverted relative to TP2]
- what happens at TP1 when TP2 is grounded (0.5)
- power dissipation in pull-up resistor for 3.3V and 5V (0.5)
- demo during lab (4)
Lab 7 (10)
- correct calculation of the required output voltage and 8 (or 16-bit) value (1 for pre-lab, 1 for report)
- listing of Verilog code for the spi module meeting course
requirements (indentation, correct use of always_ff 2)
- compilation report (1)
- screen capture of the RTL Netlist SPI module schematic (not the
top-level lab6 schematic) (1)
- demo or video of zero output (1)
- demo or video of the correct voltage output (3)
Lab 8 (10)
- pre-lab answer to questions (1)
- listing of Verilog code (indentation & file-level comments) (1)
- compilation report (1)
- RTL netlist diagram (from Quartus) (1)
- adjusted count to get 3.3V maximum display (1)
- demo showing a range of at least from 500mV to 3 V (-1 if not full
range shown, -2 if only shows ADC or only shows DMM) (5)
Quizzes
Quiz 1 (10)
Q1:
1 mark per correct answer (both width and value must be correct)
Q2:
- module statement including syntax, name, inputs, outputs, and
module/endmodule (2) (-1 per missing/incorrect element)
- assign statement including correct statement syntax, logical
condition, expression syntax, and true/false values (2) (-1 per
missing/incorrect element)
Typical Comments:
1 missing/incorrect syntax: -1
2 missing/incorrect inputs or outputs: -1
3 missing/incorrect logical condition: -1
4 missing/incorrect expression syntax: -1
5 missing/incorrect value: -1
6 does not follow course coding guidelines: -1
7 two characters
8 redundant
Quiz 2 (8)
Q1:
- correct module declaration, including inputs and outputs
- declaration of a logic signal and a 4-bit array within the module
- correct instantiation of bgen, with signal/port connections and parameter all correct
- correct instantiation of expand, with signal/port connections and parameter all correct
Note: No part marks awarded for each item above.
Common mistakes:
- using .x(y) when y is not a signal in the instantiating module
- using a declaration such as logic [3:0] x, y ; which declares both x and y to be 4-bit arrays.
- including extra (more than 3) ports in the declaration of the tgen module
- no parameter value given in the component instantiations
Typical Comments:
1 no/incorrect declaration of tgen: -1
2 no/incorrect declaration of 1- or 4-bit signals in tgen: -1
3 missing/incorrect instantiation of bgen: -1
4 missing/incorrect instantiation of expand: -1
Q2:
- correct module declaration
- state variable declaration
- always_ff with appropriate state updates
- assign to output when correct state is reached
Common mistakes:
- using two state variables (both n and sr)
- two different state updates (only one marked)
Typical Comments:
1 incorrect module declaration: -1
2 no/incorrect state variable declaration: -1
3 no/incorrect state update: -1
4 no/incorrect output: -1
Quiz 3 (8)
Q1:
-1 per missing or incorrect value
Q2:
- 1 per correct answer
Q3:
- correct SS* (1)
- correct SCLK (1)
- correct values on MOSI/MISO (2)
Typical Comments:
1 data values incorrect: -2
2 SS* misaligned with clock or wrong duration: -1
3 data misaligned with clock: -1
4 ambiguous answer: -1
5 ambiguous answer: -2
Midterm Exams
Midterm Exam 1 (12)
Q1:
- one mark per correct answer (both width and value must be correct)
Q2:
- correct module declaration, including name
- correct input and output declarations including dimensions
- two conditional operators with correct conditions
- two correct expressions for mux inputs
- assignment of result to output
Typical Comments:
1 Not an input: -1
2 Wrong conditions: -1
3 Wrong values: -1
4 Wrong assignment to output: -1
5 Wrong/missing declaration: -1
6 Syntax: should be <=
Q3:
- one mark per correct row (transition) (max 4)
- one mark deducted per incorrect row (max -4)
Typical Comments
1 missing input column: -2
2 incorrect/missing transition: -1
3 incomplete/incorrect inputs: -1
4 ambiguous answer: -4
5 missing state or inputs: -4
6 next state cannot be X: -1
Midterm Exam 2 (19)
Q1(3):
- module declaration
- always_ff
- state update
Typical Comments:
1 module declaration error: -1
2 always_ff error: -1
3 state update error: -1
Q2(6):
(marks not deducted for most syntax errors in this question)
- declares reset, clock, max[], inc[], val[]
- instantiates maxcount
- sets clock, reset, max and inc to correct initial values
- generates clock of correct period
- de-asserts reset after a delay
- terminates on correct value of val
Typical Comments:
1 reset, clock, max[], inc[], or val[] declaration error: -1
2 maxcount instantiation error: -1
3 reset, clock, max, or inc initialization error: -1
4 clock error: -1
5 reset error: -1
6 termination error: -1
clock half-period:
50 MHz: 10ns
10 MHz: 50ns
Common errors not marked incorrect:
- procedural statements not within initial or always
- incorrect ordering of procedural statements within always or initial
- statements in (somewhat) wrong order
- missing/incorrect time unit on delay (value must be correct)
- using $stop instead of $finish
- no wait() or @() before test for termination
- unnecessary code (val_t, $dumpfile/$dumpvars)
Q3(4):
- correct module declaration, including inputs (clk, reset) and output (out)
- declaration of 8-bit and 16-bit logic arrays within the module
- correct instantiation of rom
- correct instantiation of cpu
(minor errors in parameter syntax ignored due to presence of two parameters)
Typical Comments:
1 module declaration error: -1
2 array declaration error: -1
3 rom instantiation error: -1
4 cpu instantiation error: -1
5 wrong syntax
Q4(6):
(a)
- 1 mark per error
Typical Comments:
1 wrong values in answer: -2
(b)
- 1 mark for correct method
- 1 mark for correct answer
(c)
- 1 mark for correct method
- 1 mark for correct answer
Typical Comments:
1 no answer: -2
Exam
Final Exam (45)
Q1 (11)
It's impractical to verify that a handwritten exam answer will operate
correctly so this question was marked by checking for specific
features that must be present in any correct solution:
- state and timer variables of appropriate width (>=2 and >=10 bits) (2)
- you must have a variable that is 10 or more bits to implement the delay.
- if you have a state variable separate from the open/close outputs,
it must have 2 or more bits
- one or more always_ff statements with conditional assignments to one
or two state variables (2)
- correct state transitions (2)
- each expression must include the state variable(s) *and* both
inputs (opened, closed). If there are two expressions one
expression must include the value of a counter (timer), and one
must include the button. If there is one expression, the
expression must include both.
- correct outputs in each state (3)
- the code must assign two distinct values (0 and 1) each of the two
outputs
- correct timer operation (2)
- you must have an always_ff statement that assigns to the count
variable and it must include a conditional statement that both
sets it to an appropriate value and updates the current value
No partial marks were awarded; each of the above items was marked
correct or incorrect.
Typical Comments:
1 missing/incorrect state and/or timer variable(s): -2
2 missing/incorrect always_ff statement(s): -2
3 incorrect state transition condition(s): -2
4 missing/incorrect output(s): -3
5 missing/incorrect timer initialization and/or update: -2
Q2 (4)
- solve for new current from capacity and time
- solve for new power from new current and new voltage
- solve for new frequency (f2) as function of old/new voltage/frequency
- correct answer
Q3 (6)
- one mark per correct answer (both width and value must be correct)
Q4 (8)
- 6 local variables declared correctly (1)
- logic 32-bit for a,b,c , logic for clk, valid, ready
- correct instantiation of mult (1)
- mult, instance name, signals
- correct clock generated (1)
- must have 0.05us half-period
- set a and b to 11 and 2 (1)
- assert valid (1)
- wait ( ready ) [or: while ( ready !== 1 ) @(ready);] (1)
- test and print (1)
- terminate (1)
Typical Comment:
1 incorrect declaration of variables [3x32-bit, 3x1-bit]: -1
2 incorrect instantiation of mult: -1
3 incorrect clock initialization or generation: -1
4 incorrect setting of a and/or b: -1
5 incorrect setting of valid: -1
6 incorrect wait for ready to be asserted: -1
7 incorrect test for error and message print: -1
8 incorrect termination [$stop or $finish]: -1
9 incorrect testbench module declaration: -1
Q5 (2)
- solve for VOH and VOL
- correct answers
Q6 (2)
- solve for Tclock
- correct fclock
Q7 (3)
- drawn on correct signal (-3 if on both)
- correct waveform (-1 per error, max deduction -2)
Q8 (4)
- correct sample rate
- solve for SNR in dB
- solve for number of bits
- correct number of bits (an integer)
Q9 (5)
- -1 per wrong answer (maximum deduction -5)