Marking Scheme
The items below were checked. One mark was assigned for each item
unless otherwise indicated.
A red X indicates one mark was deducted.
Labs
Pn (Part n) is the code used in the corresponding Lab Comments on the
Grades page.
Note: For any solution to be considered correct the course coding
guidelines must be followed. No marks awarded otherwise (e.g. use of
sequential Verilog statements).
Lab 0
Lab 0: (0)
P1: report formatting
- is a PDF file
- has cover page with course name & number, lab number & title;
- student name & number; date
- headings for each section
P2: block diagram
- drawn by student, not RTL Netlist Viewer
- legible
- uses a multiplexer schematic symbol
- signals and ports are labelled
- bus widths (for a, b, y) are marked
P3: corrected code
- has comments at top with correct information (file name, purpose,
author's name & date)
- consistent indentation
- changed wire and reg to logic
- changed always to always_ff
- [ideally:] always_ff @(posedge clk) count <= enable ? count + 1'b1
: count ;
P4: Screen captures
- compilation report
P5: submitted video file
- a file, not a link
- video plays in browser
- properly oriented
Lab 1
- block diagram (3)
- signals labelled
- uses multiplexers with correct inputs
- correct literals in Verilog format (size, base & value)
- Verilog listing (2)
- file-level comments
- reasonable indentation (3 to 8 spaces)
- compilation report (1)
- demo (video or in lab) (4)
- incorrect orientation (-1)
- correct numbers from ID (-2 per incorrect digit)
- display for other keys (-1)
Lab 2
P.1 block diagram (3)
- bus widths labelled
- multiplexers inputs labelled
- correct literals in Verilog format (size, base & value)
P.2 Verilog listing (2.5)
- uses always_ff (1)
- file-level comments (1)
- proper indentation (between 3 and 8 spaces) (0.5)
P.3 compilation report (0.5)
P.4 demo (video or in lab) (4)
- correct orientation (-1 in wrong)
- all four digits displayed and correct (-2 per incorrect digit)
- shows both sets of 4 digits (-1 if only one)
Lab 3
P.1 Verilog listing (4)
- file level comments (0.5)
- correct indentation (0.5)
- uses always_ff (1)
- scans from top (0111) to bottom row (1110) (1)
- stops scanning if any button pressed (1) P.2 compilation report
(0.5) P.3 video (5.5)
- subtract 2 per wrong digit
- subtract 1 mark if * not right digit
- subtract 1 mark if # not right digit
Lab 4
P1. cover page (0.5) P2. compilation report (0.5) P3. Verilog code
listing with:
- file level heading (1)
- correct indentation (consistent and 3-8 spaces) (1) P4. block
diagram (RTL Netlist) (1) P5. demo of working circuit generating with
correct key (2), correct tone duration (2), and correct frequency (2)
Lab 5
[Marked PDF reports are available as Feedback in Assignment folders.]
- P1: cover page (0.5)
- P2: listing source code with file-level comments and consistent
indentation (2)
- P3: compilation report (0.5)
- P4: RTL Netlist Schematic (1)
- P5: demo (6) (reset clears (1), correct sequence unlocks (3),
incorrect sequence doesn't (2))
Lab 6a (10)
- listing of .sv file (including file header(1), indentation(0.5) and
cover page(0.5)) (2)
- RTL Netlist block diagram (1)
- screen capture of state transition diagram with at least 10 states (1)
- screen capture of 'scope display (2)
- screen capture of logic analyzer with correct student ID (2)
- screen capture of protocol analyzer with correct student ID (2)
Lab 6b (10)
- listing of .sv file (including file header(1), indentation(0.5) and
cover page(0.5)) (2)
- RTL Netlist block diagram (1)
- compilation report (1)
- video demo of correct operation (6)
Lab 7 (10)
- measured component values (R1-R3, C1-C2) (2; -0.5 per missing
component or units)
- four screen captures (4)
- table with seven measurements using three methods (3)
- photo of circuit (1)
Lab 8 (10)
- photo of circuit (2)
- screen capture of correct 3.3 to 5V converter operation (3)
- describe what happens if drain is shorted (1)
- screen captures of correct 5 to 3.3V converter (3)
- describe what happens when switch pull-up from 3.3 to 5V (1)
Lab 9 (5)
- listing of .sv file (including file header) (1)
- screen capture of simulation waveforms (1)
- screen capture of testbench transcript (3; -1 per incorrect test)
Quizzes
Quiz 1
Q1(2):
- correct module declaration syntax and array dimensions
- correct statement to generate output
Q2(4):
- 1/2 mark per correct answer
Q3(2):
- correct expressions for the two multiplexer inputs
- correct selection between the two results
Quiz 2
Q1(2)
- module declaration syntax
- parameter declaration with correct default
[Subtracted 1/2 mark if the answer included anything other than the
module declaration.]
Q2(6)
- module declaration syntax
- internal signal declaration
- two module instantiations
- correct parameter values
- legal instance names
- correct port-to-signal mappings
[In each case 0.5 marks were deducted for minor syntax errors or if
only one of two statements was correct.]
Q3(1):
- correct answer
Quiz 3
Q1(4)
- one mark per correct answer
Q2(4)
- one mark per correct answer
Q3(4)
- choose correct (max) delay to use
- use correct calculation method for clock period
- correct clock period
- correct conversion to clock frequency
Q4(3)
- one mark per correct answer
Midterm Exams
Midterm 1
Q1 (5)
- in/state/out columns
- on reset goes to first state from any other
- there are three conditional (reset not asserted) transitions to four
other states (2)
- does not transition from fourth state (unless reset asserted)
Q2 (8)
- correct state bubbles (4)
- correct state transitions (4) (-0.5 per syntax errors)
Q3 (8)
- correct module declaration (logic, in, out, clock) (1)
- correct state variable declaration (1)
- correct always_ff @(posedge clk) (1)
- correct transitions (4) (1 or 2 marks if mostly correct but syntax
and/or logic wrong)
- correctly output only on state D (1)
Midterm 2
Q1 (7)
- correct top module declaration
- declaration of intermediate signals
- three correct module instantiations (3)
- correct parameter values (2)
Q2 (2)
- syntax (type, dimensions, initialization)
- values (0,1,4,9,16)
Q3 (3)
- one per correct answer (3)
Q4 (3)
- -0.5 mark per incorrect value
Q5 (2)
- correct direction (MISO or MOSI)
- correct value (in hex)
Final Exam
Q 1 (4)
- correct module declaration
- an assign statement
- correct use of conditional operator
- correct use of concatenation operator
Q 2 (4)
- correct module declaration
- correct always_ff
- correct reset
- correct increment
Q 3 (4)
- correct module declaration
- correct always_ff
- correct conditional expression
- correct sum
Q 4 (5)
- -0.5 mark per incorrect value
Q 5 (3)
- -0.5 mark per incorrect value
Q 6 (4)
- ignores start & stop bits
- correct bit order (lsb first)
- correct bit polarity (low = 1)
- correct verilog format (8'hXX)
Q 7 (3)
- correct clock period
- use correct calculation method for tPD
- correct answer
Q 8 (4)
- one per correct answer
Q 9 (2)
- one per correct answer
Q 10 (2)
- correct formula
- correct answer
Q 11 (1)
- correct answer