Marking Scheme

Only the items below were checked.
One mark was assigned for each item unless otherwise indicated.
A red X is used where one mark was deducted. A green checkmark shows the answer is correct.

Labs

Note: For any solution to be considered correct the course coding guidelines must be followed. No marks awarded otherwise (e.g. use of sequential Verilog statements).


                             Lab 0: (0)

Report formatting (2)
  - has cover page with course name & number, lab number & title;
  - student name & number; date

Block diagram (5)
  - drawn by student, not RTL Netlist Viewer
  - legible
  - uses a multiplexer schematic symbol
  - signals and ports are labelled
  - bus widths (for a, b, y) are marked

Corrected code (5)
  - has comments at top with correct information (file name, purpose,
    author's name & date)
  - consistent indentation
  - changed wire and reg to logic
  - changed always to always_ff
  - single assignment in always_ff

Screen captures (1)
  - includes a compilation report
  
Submitted video file (3)
  - a file, not a link (-1)
  - video plays in browser (-1)
  - properly oriented (-1)


                              Lab 1 (10)

- cover page (1)
- block diagram matching your code (1)
- listing matching your demo (1)
- compilation listing matching your code (1)
- demo (video or in lab) (6)
  - wrong orientation (-1)
  - three correct numbers for keys (1, 2 and 3) as per ID (-2 per incorrect digit)
  - no display for other keys (A, 5, 9 and D) (-1)

- half marks deducted if report and video guidelines not followed
- no marks if submission is the wrong format

                                Lab 2 (10)

- cover page (1)
- listing conforms to coding guidelines (2)
  - file-level comments (0.5)
  - consistent indentation (1)
  - use of always_ff with single non-blocking assignment (0.5)
- compilation report (1)
- correct digits displayed when 1 pressed (2, -1 for each incorrect digit)
- correct digits displayed when 2 pressed (2, -1 for each incorrect digit)
- digits displayed for pressing 1 and 2 but not for 3 or 5 (1)
- correct orientation (1)

                              Lab 3 (10)


- a successful initial demo (3 marks)
- a successful demo of the requested change (3 marks)
- report (4 marks):
  - a listing of the initial design (only if successfully demonstrated in the lab)
  - proper file-level comments and indentation of the above code
  - a listing of the modified design (if successfully demonstrated in the lab)
  - a compilation report (of either design)


                               Lab 4 (10)

- cover page (0.5)
- compilation report (0.5)
- Verilog code listing with:
    - file level heading (1)
    - correct indentation (consistent and 3-8 spaces) (1)
- block diagram (RTL Netlist) (1)
- demo of working circuit generating with:
  - correct key (2)
  - correct tone duration (2)
  - and correct frequency (2)


                              Lab 5 (10)

- listing of DUT .sv file (2, 1 if if correct indentation or missing file-level comments)
- listing of testbench .sv file (2, 1 if incorrect indentation or missing file-level comments)
- screen capture of simulation waveforms (1)
- screen capture of testbench transcript (1)
- correct results (4):
  - -4 if initial register value does not match student ID
  - -2 if shift register value does not "wrap around" to initial value after 15 clock cycles
  - -1 if last test vector does not print error message

Typical Comments:
1 file-level comments or indentation missing/incorrect: -1
2 missing or incomplete simulation waveforms: -1
3 missing/incomplete transcript: -1
4 wrong initial register value: -4
5 not enough or incorrect test vectors/results: -2
6 missing error message at end of simulation: -1
7 wrong formatting for a listing (line spacing or font)

                              Lab 6 (10)

- cover page (0.5)
- listing source code with file-level comments (1)
- consistent indentation (1)
- compilation report (0.5)
- RTL Netlist Schematic (1)
- demo (6)
  - reset clears (1)
  - correct sequence unlocks (3)
  - incorrect sequence doesn't (2)

                              Lab 7 (10)

- what happens at TP1 when TP2 is grounded (1)
- power dissipation in pull-up resistor for 3.3V and 5V (1=2x0.5)
- three screen captures (6)
- demo during lab (2)

                              Lab 8 (10)

- correct calculation of the required output voltage and 16-bit value
  (2)
- listing of Verilog code for the spi module meeting course
  requirements (comments and indentation, 1)
- compilation report (1)
- screen capture of the RTL Netlist SPI module schematic (not the
  top-level lab6 schematic) (1)
- demo or video of zero output (1)
- demo or video of the correct voltage output (4)

Quizzes


                                Quiz 1

Q1:
    - module statement syntax
    - inputs and outputs
    - assign statement and expression

    Typical Comments:
    module statement incorrect: -1
    assign statement incorrect: -1
    module syntax: -1
    syntax...
    
Q2:
    - correct width, base and value (-1 for each wrong)

Q3:
    - one mark per correct answer (both width and value must be correct)

Q4:
   - two muxes
   - correct control and inputs (unambiguously labelled)
   - correct mux order

    Typical Comments:
    no multiplexers: -1
    wrong multiplexer order: -1
    not- or mis-labelled inputs: -1
    wrong or missing select input: -1
    no answer: -3

                                Quiz 2

Q1: -1 per wrong answer
Q2: -0.5 per wrong value
Q3: -1 per wrong value

                                Quiz 3 (7)

Q1:
- tSU and tCO correct
- period (tCLOCK) correct
- correct max tPD calculation and result

Typical Comments:
1 wrong tSU or tCO: -1
2 no work shown: -3
3 tPD wrong: -1
4 wrong Tclock: -1
5 wrong formula: -1

Q2:
- correct PD at lower frequency
- correct average

Typical Comments:
1 wrong units: -1
2 wrong average power: -1
3 calculation error: -1
4 obviously wrong answer (e.g. power >50mW): -2
5 no answer: -2

Q3:
- correct SNR
- correct ENOB

Typical Comments:
1 wrong equation: -0.5
2 arithmetic error: -1
3 no answer: -2
4 algebra error: -1

Exams


                              Midterm 1 (17)

Q1 (5):

- one mark per correct answer (both width and value must be correct)

Q2 (4):

- module declaration with the required inputs and outputs
- declaration of an 8-bit 'count' array 
- always_ff assigning incrementing 'count'
- correct value assigned to 'out'

Typical Comments:
1 count is not an input or output: -1
2 counting incorrect: -0.5
3 assignment to out incorrect: -0.5
4 no assignment to out: -1
5 no declaration of count array: -1
6 mux inputs are 1 and 0, not enable and w: -0.5
7 module declaration incorrect: -0.5

Q3 (4):

- 4 or fewer different states: -4
  (since the other requirements can't be met)
- incorrect or missing output table: -2
- per incorrect state transition: -1
- wrong type of state encoding: -1

Typical Comments:
1 has 4 or fewer different states: -4
2 incorrect or missing output table: -2
3 incorrect/missing transition: -1
4 wrong type of state encoding: -1

[many solutions used the output as the state]

Q4 (4):

- module and state variable declarations
- resets when clear asserted
- three correct transition conditions
- assign 1 to output only in fourth state.

Typical Comments:
1 missing or incorrect state variable declaration: -1
2 missing state variable: -1
3 syntax: -0.5
4 missing or incorrect assignment to output: -1
5 missing or incorrect state transition: -1
6 transition conditions don't include state: -1
7 number on second line is the output, not part of the state value.

                              Midterm 2 (14)

Q1 (2)

- correct direction
- correct value

Typical Comments:
1 ambigous answer: -2
2 wrong answer syntax: -1
3 wrong value: -1
4 wrong direction: -1

Q2 (3)

- one mark per correct answer [(250 kHz, 0, 5) or (125 kHz, 1, 4)

Q3 (4)

- module declaration with name, inputs and outputs
- declaration of three internal signals
- instantiation of two bcnt modules
- correct signal-to-port mappings

Typical Comments:
1 no signals declared: -1
2 no such signal: -1
3 wrong width: -0.5
4 ambiguous solution: -4
5 syntax error: -0.5
6 no answer: -4
7 not enough internal signals: -1
8 incorrect mapping: -1

Q4 (5)

- state register declaration(s) of at least 2 bits
- state always reset when reset asserted
- output is 0 in this state
- other state transitions conditional on in
- output is 1 some state(s)

Typical Comments:
1 not enough state declared: -1
2 no or incorrect reset: -1
3 unconditional state change: -1
4 wrong output when [not] reset: -1
5 wrong or no output: -2
6 syntax: -0.5
7 wrong output: -1
8 wrong state transitions: -1
9 no solution: -5


                              Final Exam

Q1 (5)

- module declaration with clock and reset inputs, n output
- always_ff for 'c' register
- correct conditional expression to reset/decrement
- always_ff for 'n' register
- correct conditional expression to reset/increment

* Comments:
1 c is not an output: -0.5
2 already declared as an input: -0.5
3 does not match schematic: -0.5
4 syntax: -0.5
5 no answer: -5

Q2 (5)

- 1 mark per correct answer (both width and value)

Q3 (2)

- correct calculation of available setup time
- correct conclusion

* Comments:
1 calculation error: -1
2 no/incorrect calculation: -1
3 no work shown to support answer: -1
4 incorrect rounding: -0.5
5 inequality backwards: -0.5

Q4 (4)

- module declaration
- correct reset
- correct state transitions (2)

* Comments:
1 module has an output: -2
2 no declaration of state register: -1
3 no reset: -1
4 syntax: -0.5
5 wrong state encodings: -2
6 wrong inputs: -1
7 state register is wrong size: -1
8 transitions not conditioned on state: -2
9 no/wrong default transition: -1

Q5 (2)

- one mark per correct answer

Q6 (2)

- correct method
- correct answer

* Comments:
1 used step size (resolution) instead of error: -1
2 calculation error: -1

Q7 (1)

- correct answer

Q8 (2)

- 1 mark per correct answer

Q9 (2)

- correct power at 1 MHz
- correct average

Q10 (6)

- one mark per correct answer

* Comments:
1 ambiguous answer: -2
2 calculation error: -1