Version 2: corrected testbench.
Example video.
If you used the same pinouts as in the lab notes you can program your CPLD with this file to check that your hardware is working correctly.
Rename this file to lab8.sv and add your code to the SPI module as noted in the comments.
Pin assignments corresponding to those shown in the lab notes.
Test vectors for the testbench included in lab8.sv.
Note: download and install MAX II instead of Cyclone IV device support files.
Note: select the EPM240T100C5 device (you can filter on the MAX II device family, TFQP package, 100 pin and speed grade 5).
There was no Lecture 3, these are the answers to the exercises for Lecture 4 (Applications of State Machines).
Version 2 - reversed the first two transition conditions for the binary encoding version of Question 4.
Version 3 - reversed the labelling of the two solutions for Question 1.
These may or may not be the datasheets for the components we will be using.
Links to some additional [System] Verilog resources.