Marking Scheme
The items below were checked. One mark was assigned for each item
unless otherwise indicated.
A red X indicates one mark was deducted.
Labs
Note: For any solution to be considered correct the course coding
guidelines must be followed. No marks awarded otherwise (e.g. use of
sequential Verilog statements).
Lab 0
Lab 0: (0)
Report formatting (4, -1 for each error)
- is a PDF file
- has cover page with course name & number, lab number & title;
- student name & number; date
- headings for each section
Block diagram (5, -1 for each)
- drawn by student, not RTL Netlist Viewer
- legible
- uses a multiplexer schematic symbol
- signals and ports are labelled
- bus widths (for a, b, y) are marked
Corrected code (5, -1 for each)
- has comments at top with correct information (file name, purpose,
author's name & date)
- consistent indentation
- changed wire and reg to logic
- changed always to always_ff
- single assignment in always_ff
Screen captures (-1)
- includes a compilation report
Submitted video file (3, if applicable)
- a file, not a link (-1)
- video plays in browser (-1)
- properly oriented (-1)
Lab 1
- block diagram (3)
- signals labelled
- uses multiplexers with correct inputs
- correct literals in Verilog format (size, base & value)
- Verilog listing (2)
- file-level comments
- reasonable indentation (3 to 8 spaces)
- compilation report (1)
- demo (video or in lab) (4)
- incorrect orientation (-1)
- three correct numbers as per ID (-2 per incorrect digit)
- no display for other keys (-1)
Lab 2
Cover page (1)
Verilog listing (2.5)
- uses always_ff (1)
- file-level comments (1)
- proper indentation (between 3 and 8 spaces) (0.5)
Compilation Report (0.5)
Demo (video or in lab) (3)
- correct orientation (-1 if wrong)
- all four digits displayed and correct (-1 per incorrect digit)
- shows both sets of 4 digits (-1 if only one)
Lab 3
Verilog listing (5)
- file level comments (0.5)
- correct indentation (0.5)
- uses always_ff (1)
- scans from bottom row (1110) to top (0111) (2)
- stops scanning if any button pressed (1)
Compilation report (0.5)
Video/Demo (6.5)
- subtract 1 mark for wrong display orientation in the video
- subtract 1 mark for not testing letters (A-D)
- subtract 2 per wrong digit
- subtract 1 mark if * not right digit
- subtract 1 mark if # not right digit
Lab 4 (12)
Report (3)
- cover page (0.5)
- correctly calculated button, frequency and duration (1)
- block diagram matching the submitted Verilog listing (hand drawn)
(1)
- block diagram (as produced by Quartus RTL netlist) (0.5)
Verilog code listing showing: (2)
- file level heading (1)
- correct indentation (consistent and 3-8 spaces) (1)
Compilation report (0.5)
Demo of working circuit generating (6.5)
- correct key causes a tone (0.5),
- tone starts when button pressed (not when released) (1)
- correct tone duration independent of button press duration (1)
- correct tone duration (2), and
- correct frequency (2)
Lab 5 (10)
- listing of the test vector file with correct student number, (2, -1
per error)
- listing of DUT .sv file (2, 1 if incorrect indentation or missing
file-level comments)
- listing of testbench .sv file (1, 0.5 if incorrect indentation or
missing file-level comments)
- screen capture of simulation waveforms (1)
- screen capture of testbench transcript (1)
- correct results (3; -1 per mismatch)
Lab 6 (9)
- correct calculation of the required output voltage (1)
- listing of Verilog code for the spi module meeting course
requirements (comments and indentation, 1)
- compilation report (1)
- screen capture of the spi module schematic (not the top-level lab6
schematic) (1)
- demo or video of the correct voltage output (5)
Lab 7 (10)
- A description of what happens at TP1 when you ground TP2 (1)
- A description of what happens when you switch the pull-up on TP3
from 5~V to 3.3~V (1)
- A screen capture showing the cursor and 'scope measurement results
for the threshold voltages (1)
- Screen captures showing the cursor and 'scope measurement results
for the rise and fall times (2)
- Screen captures showing the cursor and 'scope measurement results
for the low and high pulse widths (2)
- Demo of circuit to instructor in the lab (3)
- If you did not demo the lab during the assigned lab session (-1)
Lab 8 (8)
- listing of Verilog code (indentation & file-level comments) (1)
- compilation report (1)
- RTL netlist diagram (from Quartus) (1)
- table with hex ADC result, DMM voltages & error (2, 1 marks if <4
values or missing column)
- demo (3, -1 if not full range shown, -2 if only shows ADC or only
shows DMM)
Quizzes
Quiz 1
Q1 (3 marks)
- keywords and syntax
- input
- output
Q2 (3 marks)
- length
- base
- value
Q3 (5 marks)
- one mark per fully correct answer; no part marks
Q4 (4 marks)
- correct type of statement & syntax
- correct control signal or clock
- correct input(s)
- correct output
Quiz 2 (7)
Q1 (5)
- correct max length (5 - the sequence includes the 0's)
- correct min length (4)
[Due to the difficulty of the question, the details of the state
transition diagram were not marked. Instead marks were awarded for:]
- a diagram with three or more states
- three or more correct transitions (transitions where `in' is
compared to an array were marked incorrect because `in' is a scalar)
- there are three or more states and the out (or out_n) is 1 (or 0)
for one or more plausible end-of-sequence state(s)
Q2 (2)
- correct logic level (or H or L; not 0 or 1 or T or F)
- correct value (0 or 1'b0 or 1 or 1'b1; not T or F or H or L)
Quiz 3 (7) Q1 (1 marks)
- result and justification
Q2 (2 marks)
- correct method
- correct result
Q3 (2 marks)
- correct method
- correct result
Q4 (2 marks)
- correct result
- plausible justification
Midterm Exams
Midterm 1
Q1 (2)
- correct syntax
- correct values
Q2 (2)
- correct number of bits
- correct starting value
Q3 (4)
- ymod module declaration
- temporary signal declaration
- instantiation of ex63 module
- an assign or always_ff statement
Q4 (4)
- line(s) for reset (1)
- lines for other transitions (3)
Q5 (4)
- labelled states
- reset transitions
- other transitions (2)
Midterm 2
Q1(5)
- always_ff
- correct reset
- correct switch to 010
- correct switch to 001
- correct output
Q2(2)
- one mark per correct answer
Q3(4)
- module declaration with name, inputs and outputs
- declaration of internal signal (if used)
- instantiation of two quad modules
- correct signal-to-port mappings
- subtract 0.5 marks for minor syntax errors
Q4(4)
- one mark for each of the required features
- 0 deducted for minor syntax errors (e.g. using == instead of =)
- 0.5 deducted in each part for each minor error, for example:
- always inside an initial block or wait/if/assignment outside of
initial or always
- missing begin/end
- wrong clock period (if a clock was used)
- not adding n+1 to n
- no marks awarded in a section if more than one minor error
Q4(2)
- used correct waveform
- correct value
Final Exam
Q1(6)
- module declaration (1)
- parameter declaration (1)
- three conditional operators (1)
- four expressions involving A (and B) (2)
- register (1)
Q2(8)
- one mark per correct answer (must have correct length and value)
Q3(5)
- correct choice of MISO or MOSI
- correct SS duration
- correct phase of sclk vs data
- correct data values
- correct data bit order
Q4(2)
- noise margins
- correct operation
Q5(4)
- clock period
- use of maximum propagation delay
- computing slack
- conclusion
Q6(2)
- one mark per correct answer
Q7(3)
- 3 ports
- 2 muxes
- a 16-bit register
Q8(3)
- one mark per correct answer (the value should be within half a
division)
Q9(5)
- one per correct transition
- -1 per incorrect transition