Version 2: Simplified rules for block diagrams.
Version 2: Re-ordered and revised sections on Arrays of Arrays and Statements.
Revision 2: Changed SPI example to msb-first; added state to controller timing diagram.
If you used the same pinouts as in the lab notes you can program your CPLD with this file to check that your hardware is working correctly.
Example video.
You'll need to add this file to your project to generate a 200 Hz clock.
Program this file to test your hardware.
Demonstration video for Lab 2.
Note that this lab is subtly different than last year's Lab 3.
Spreadsheet to generate test vectors.
Revision 2: added bypass capacitor, MISO delay to block diagram, simulation example, and use of keypad 2 to reset.
Revision 3: Revised November 8 to fix timing of shift control signal relative to state (it was early by one clock period). Revised again to fix MISO timing offset (not used in this lab) and remove redundant test vector signals.
Revision 3 (to match Revision 3 of lab6-incomplete).
Revision 3 (to match Revision 3 of lab6.sv).
Version 2: View inverted waveforms on TP1 and TP3 (not TP2).
Rename to lab8.sv and add your code to this file.
You can import pin assignments and other settings from this file.
Note: download and install MAX II instead of Cyclone IV device support files.
Note: select the EPM240T100C5 device (you can filter on the MAX II device family, TFQP package, 100 pin and speed grade 5).
Revision 2.
Revision 2: Added reset!=0 transition conditions in Question 5.
Links to some additional [System] Verilog resources.