Marking Scheme
The items below were checked. The marks assigned for each item are as
shown.
Midterm Exams
Midterm 1
Q1(6): -1 mark per error (maximum of -6)
Q2(5): 1 mark for each of: module keyword and name, use of logic type,
use of input and output, array port, correct index order.
Q3(5): 1 mark for each of: assign keyword, output signal, condition
and tertiary operator, true expression, false value.
Q4(6): two marks for each of three correct answers; Only the T/F
values in the middle two rows and the 0 in the third row were marked
since the context (I/O or logical expression) was not given.
Q5(6): one mark for each correct value. No marks if a value spanned
more than one clock period.
Q6(9)
(a) (3 marks)
- 4 states appropriate labelled
- correct state transitions for reset
- correct state transitions for enable and not reset
(b) (6 marks)
- bits_next (or other required) signal declaration(s)
- assign(ment) to bits_next (or other state variable)
- correctly implements reset
- correctly implements growing/shrinking the number of bits (2, 1 mark
per transition) (no mark deducted if *one* transition is wrong but
agrees with diagram)
- correct always_ff statement
Q7(3): one mark subtracted per mistake (maximum of -3). 8 or 4 allowed
for size of slice.
Midterm 2
Q1(6): Timer design
- counter declaration with sufficient number of bits (>=[3:0] for 10,
>=[4:0] for 30us)
- counter set or reset to appropriate value only when run is asserted
(should not count continously)
- count is decremented only during pulse duration
- always_ff statement to create a count register
- pulse output is set according to count value (or state)
- correct pulse duration would be generated
Q2(4): SPI interface
- data is on MISO when read from sensor, on MOSI when write to sensor
- correct bits
- correct bit order
- correct decimal value (191 read from sensor, 211 writen to sensor)
Q3(3): Timing analysis
- correct available setup time (12ns)
- correct clock period (25 or 40ns)
- correct maximum propagation delay (6ns for 40 MHz, 26ns for 25 MHz)
Q4(5): Memory terminology
- one mark per correct answer - 8k = 8192/65536; 16k=16384/131,072 -
Yes for write, No for read. - No for flash, Yes for DRAM. - No.
Final Exam
Q1
- output changes at rising edge of clock
- resets to right value
- increments by right amount
Q2
- 0.5 marks per correct answer
Q3
- -0.5 mark per error (maximum deduction of 1 mark)
Q4: decode an SPI waveform
- correct direction
- correct value
Q5
- correct reset
- correct increment (note: {2'b10,1} is 2'b01 not 2'b11)
- does not go past value 3 (most common error)
- correct register
Q6
- one mark for method
- one mark for correct answer
Q7: memory design
(everyone missed that the memory size was 1 MByte, not 1 MWord)
- one mark per correct answer
Q8: CMOS logic
- one mark for a (fully) correct answer Q9: terminology
- one mark per correct answer Q10:
- one mark for a correct answer Q11: power consumption
- one mark per correct answer
Q9: terminology
- one mark per correct answer
Q10:
- one mark for a correct answer
Q11: power consumption
- one mark per correct answer
Labs
Pn is the reference used in the Lab Comments on the Grades page.
Note: A pre-requisite for any solution to be considered correct is
that the course coding guidelines were followed. No marks will be
awarded if the output is correct but the design does not meet
requirements (e.g. use of sequential Verilog statements).
Lab 0: (0)
P1: report formatting
- is a PDF file
- has cover page with course name & number, lab number & title;
- student name & number; date
- headings for each section
P2: block diagram
- drawn by student, not RTL Netlist Viewer
- legible
- uses symbols similar to those used in lecture notes
- signals and ports are labelled
- bus widths are marked if greater than 1
P3: corrected code
- has comments at top with correct information (file name, purpose,
author's name & date)
- consistent indentation
P4: Screen captures
- compilation report
- modelsim
- signaltap
P5: submitted video file
- a file, not a link
- video plays in browser
- video resolution not over 720p
- properly oriented
Lab 1
PreLab (2) (prelab_mark):
- block diagram that meets requirements (1)
- listing of your Verilog code that (tries to) implement the lab
requirements (1)
Lab (5) (lab_mark):
- Verilog code listing (1)
- compilation report (1)
- demo that meets requirements (3)
Note: The Pre-Lab will not be marked if you successfully complete the
lab.
Your Lab 1 mark (out of 1) will be computed as:
assigned_lab_mark = ( demo_mark == 3 ) ? ( lab_mark/5 ) : (
lab_mark + prelab_mark ) / 7
Lab 2
Pre-Lab (2)
- block diagram
- Verilog listing
Lab Report (6)
- listing of Verilog code complying with course coding guidelines and
report complies with course report guidelines (1.5)
- screen capture of compilation report (0.5)
- demonstration of correct operation (4)
- 1 mark deducted for not complying with video guidelines
- 2 marks deducted for minor display errors (e.g. wrong order or >=
half correct)
- 4 marks deduced if display is wrong (e.g. wrong or no numbers
displayed)
assigned_lab_mark = ( demo_mark >= 3 ) ? ( report_mark/6 ) : (
lab_mark + prelab_mark ) / 8
Lab 3
Pre-Lab (2)
- state transition diagram (1)
- Verilog code (1)
Lab Report (10)
- Verilog listing (1)
- screen capture of Signal Tap showing:
- correct order for student's ID (2)
- at least five values on row (0.5)
- compilation report (0.5)
- video (6)
- (subtract 3 marks if 1 digit is wrong)
assigned_lab_mark = ( video_mark >= 6 ) ? ( report_mark/10 ) : (
lab_mark + prelab_mark ) / 12
Lab 4 (10)
- cover page and file comment header (1)
- block diagram (1)
- Verilog code listing with consistent indentation and correct count
value for student ID (1, 0.5 if frequency is twice)
- block diagram (RTL Netlist) (1)
- demo of working circuit generating a tone (6)
Lab 5 (10)
- P1: block diagram (1)
- P2: schematic generated by "RTL Netlist" (1)
- P3: compilation report (1)
- P4: source code with file-level comments and consistent indentation
(1)
- P5: demo (6) (reset (1), correct modulo (3), carries work(1), all
keys increment a digit(1))
Lab 6 (10)
- listing of .sv file (including file header) (1)
- RTL Netlist block diagram (1)
- screen capture of state transition diagram with at least 10 states
(1)
- screen capture of 'scope display (2)
- screen capture of logic analyzer with correct student ID (2)
- screen capture of protocol analyzer with correct student ID (3)
- 3 marks were deducted if the code uses sequential Verilog statements
(e.g. case, if/else) or if it does not generate a state machine
Lab 7 (5)
- listing of .sv file (including file header) (1)
- screen capture of simulation waveforms (1)
- screen capture of testbench transcript (3; -1 per incorrect test)
Lab 8 (10)
- measured component values (R1-R3, C1-C2) (2; -0.5 per missing
component or units)
- four screen captures (4)
- table with measurements using three methods (3)
- photo of circuit (1)
Quizzes
Quiz 1 (13)
Q1 (3):
- module keyword and module name
- correct input or output
- correct bit widths and bit order
Q2 (3)
- assign keyword
- correct signal names
- correct operator
Q3 (3)
- correct width
- correct base
- correct value
Q4 (4)
- assign keyword
- conditional operator
- correct signal names
- correct values
Quiz 2
Q1(2): 1 mark per correct letter, -1 for incorrect letter Q2(2): 1 for
each correct value with units Q3(1): 1 for correct answer Q4(3): 1 for
each correct value-solutions
Quiz 3(6)
Q1(2): 1 for correct bytes (32768[+1] or 16384[+1], 1 for correct
words (half of no. of bytes) Q2(1): 1 for correct value 0x2000
is 13bits, 0x1000 is 12bits Q3(1): 1 for correct answer
(functional), 0 for any other answer Q4(2): 1 for correct VOH
(1.5=1.2+0.3 or 1 for correct VOL (0.2=0.5-0.3 or