ELEX 2117 - Digital Techniques 2

• Announcements
• Course Information
• ELEX 2117 Course Information
• marking
• Software Installation and Use

  Revised September 25.

• Coding Guidelines
• Report and Video Guidelines
• ELEX2117Template.dotx

  Microsoft WordTemplate you can use for pre-lab and lab reports.

• ELEX2117Usage.docx

  Instructions and examples on how to use the report template.

• Lectures
• Lecture 1 - Introduction to Digital Design with Verilog HDL

  revised Sept. 15

• Lecture 2 - Flip-Flops and Registers
• Lecture 3 - State Machines
• Lecture 4 - More System Verilog

  Revision 2: added examples in Modules section.

• Lecture 5 - Common Circuits
• Lecture 6 - Interfaces
• Lecture 7 - Timing Analysis
• Lecture 8 - Memory System Design
• Lecture 9 - Verification
• Lecture 10 - Implementation of Digital Logic Circuits
• Lecture 11 - Programmable Logic Applications and Architectures
• Labs
• Lab 0 - Practice Lab

  Version 2: corrected syntax errors in sample code.

• debounce.sv
• Lab 1 - Combinational Logic Design with Verilog

  Revision 2: Only top keypad row to be set low.

• lab1.sof

  If you used the same pins as in the lab instructions you can program the FPGA with this file to check that your hardware is working properly.

• lab1demo.mp4

  Example of required behaviour.

• Lab 2 - Sequential Logic Design with Verilog
• lab2.sof

  You can program the FPGA with this file to check that your hardware is working properly.

• lab2demo.mp4

  Example of required behaviour.

• Lab 3 - Matrix Keypad Decoder
• lab3demo.mp4

  Example of required behaviour.

• lab3.sof

  You can program the FPGA with this file to check that your hardware is working properly.

• Lab 4 - Timers and Frequency Dividers

  Revision 2: added more details and state transition diagram to Specifications section.

• lab4demo.mp4

  Example of required behaviour.

• lab4.sof

  You can program the FPGA with this file to check that your hardware is working properly.

• lab4.sdc

  You can add this file to your project to define the clock rate for the timing analyzer (to be covered later).

• Lab 5 - Modulo‑n Counters
• lab5demo.mp4

  Example of required behaviour.

• lab5.sof

  You can program the FPGA with this file to check that your hardware is working properly.

• lab5.qar

  Quartus project archive.

• Lab 6 - Asynchronous Serial Interface
• lab6.qar
• lab6.sof
• Lab 7 - Simulation
• lab7_tb.sv
• lab7.sv
• lab7testdata.zip
• Lab 8 - Digital Waveform Measurement
• Videos
• Installing Quartus
• Using Quartus for Logic Synthesis
• Simulation with Modelsim
• Using the SignalTap Logic Analyzer
• Exercise Answers
• lec1-exercises
• lec2-exercises
• lec3-exercises
• lec4-exercises
• lec5-exercises
• lec6-exercises
• lec7-exercises
• lec8-exercises
• lec9-exercises
• lec10-exercises
• Exams
• Quiz 1
• Solutions to Quiz 1

  Revised level width in detect module definition of Question 1 to be 12 bits instead of 16.

• Midterm 1
• Solutions to Midterm 1

  Revision 3.

• Quiz 2
• Solutions to Quiz 2
• Midterm 2
• Solutions to Midterm 2
• Quiz 3
• Solutions to Quiz 3
• Final Exam
• Solutions to Final Exam
• Datasheets

  These may or may not be the datasheets for the components we will be using.

• EP4CE6E22C8N FGPA Boards Schematic
• FJ-5463 4-digit 7-segment LED Display
• "USB-Blaster" Schematic (STM32 version)
• Resources
• Verilog
• Verilog Papers

  Links to some additional [System] Verilog resources.

• Other
• Parts Kits Contents
• Student Evaluations