The numbers in parentheses indicate the number of marked items (1 mark each). Quizzes [The quiz marking scheme is available on Learning Hub.] Labs Lab 1 (5) One mark is awarded for each of the following: - If you submitted a PDF document containing the four required identification items (name, ID, course, lab) - If the PDF document contains a (non-trival) Verilog listing that is "easy to read". For this lab it can be a screen capture and does need not have syntax highlighting. Listings made by taking a photo of a monitor are unlikely to be "easy to read". - The Verilog code is indented with correct nesting and 'end's are indented the same as the line with the corresponding begin. - If the PDF document includes a screen capture of a compilation report that matches the code you submitted. - Submitting a video showing the correct four outputs for your student number. Lab 2 (6) - Verilog follows coding guidelines, specifically: - complete comments at beginning of the file (1) - proper indentation (1) - RTL diagram and compilation reports included (1) - video demonstrates reset (1) - video shows correct student number (1) - video shows correct operation at end of number (1) Lab 3 (4) - some Verilog source code showing an attempt at a solution, even if it’s wrong - including a PDF with the RTL netlist - a video showing any sort of tone being generated - the tones are at approximately the correct frequencies for the student number (by ear) and the left/right buttons produce the higher/lower frequencies in the correct order Lab 4 (4) - included a PDF file with Verilog listings - calculate correct clock divider value for their student number - compilation report (1/2) and PDF of netlist (1/2) - photo of results showing last 4 digits of their student number Lab 5 (4) - submitted PDF with Verilog listing with file-level comments (1) - Verilog follows coding guideline restrictions on no sequential statements (except assignment withing always_ff) (1) - a video showing any digits changing (0.5) - a video showing up, down counts at correct rates and resets (1.5) Lab 6 (5) - submitted PDF with Verilog listing (1) - a video showing any digits changing (1) - a video showing up (1) and down (1) - video shows count returning to original value when pointer is back at center (1) Lab 7 (5) - PDF with identification and listing of a reasonable attempt at an .sv file (2) - RTL netlist PDF (1) - report includes 'scope, logic analyzer and protocol analyzer screen captures (1) - video showing: - value on display is reset to the correct secret number (1) - value on display changes to the correct logical inverse of the secret number (1) Lab 8 (3) - P1: first 200 ns showing module inputs and outputs (1) - P2: with all signals defined by the end of 200 ns (1) - P3: complete simulation showing counter and data (shift) register (> 25us) (1) Lab 9 (10) - P1: a PDF file with ID (4 items) (1 mark) - P2: complete table of component values with at least 3 columns (reference designator, value and units) and 6 rows (R1, R2, R3, C1, C2, D1) and reasonable values (1 mark for a table, 2 marks if complete) - P3: four screen captures (threshold, rise time, fall time, duty-cycle/period) (4 marks) - P4: summary table with at least 5 columns (measurement type, graticule measurement, cursors measurement, "Measurement" measurement, units) and 7 rows (7 different measurements) (1 mark for table, 2 marks if complete) - P5: photograph of circuit (1 mark) Midterm Exam 1 Question 1 (2) - input logic / output logic first - number of bits - bit order - order & number of variables Question 2 (..) Question 3 (..) Question 4 (..) Midterm Exam 2 Question 1 (..) Question 2 (..) Question 3 (..) Question 4 (..) Final Exam -