A Simple Cadence Place & Route Tutorial

This document will provide a quick run-through of the Cadence place and route system on a simple schematic. The example circuit which is used can be found in the EXAMPLES library when using the technology CMOS4S.

Startup

You should create a Cadence library in your own file space and copy the following cells to your library:

PR_adder_top
adder_16_bit
full_adder_2
half_adder

The Top-level schematic

The top level schematic of your design (the adder_16_bit cell in this example) will be just below the level of the completed chip - it will contain all the circuitry which defines your design with the exception of the I/O pads which will be bonded to the package (ie the DIP or the PGA package).

Once the top level schematic is completed (and you have naturally simulated to the point where you are convinced the design is perfect), you should create a symbol for your design. Once the symbol is created, create a new cell (in this example, the PR_adder_top cell)- this will be the cell on which Place & Route is run.

The Place & Route schematic

The place & route schematic will contain the following:

A single symbol instance of the top-level schematic of your design (adder_16_bit).
I/O pads for each input/output of your design.
Ground and Power pads

In the cell library for the CMOS4S process, there are several versions of the I/O pads:

The wide pads are marked with a trailing .w, as in gndcore.w
The narrow pads are marked with a trailing .n as in gndcore.n
The super narrow pads are marked with a trailing .sn. You are not likely to be using these pads, as special permission is required for their use.

In the case of CMOS4S, separate ground/power pads must be used for the core circuitry (your design) and for the I/O ring (the I/O pads themselves). You need to add 4 cells to supply power & ground to your chip:

A gndcore.X the ground for the core circuitry
A gndring.X the ground for the I/O ring
A vddcore.X to supply power to the core circuitry
A vddring.X to supply power to the I/O ring

You will use X='n' or X='w.' Naturally the signal pads must be of the same type (wide or narrow) as the power and ground pads.

The example schematic, PR_adder_top uses the wide pads:

Top level Place & Route schematic

Check and Save the place and route schematic. Now you are ready to place and route the chip.

Running Place & Route

Follow these steps when creating a CMOS4S chip layout:

Select Tools->Floorplan/Schematics. This will create a new pull-down menu titled Floorplan.
Select Floorplan->Hierarchy Browser.... A form pops up into which you can enter the name of a design. The default is the design in the current window, which is generally the one on which you want to run the Hierarchy Browser. Select OK. The Hierarchy Browser window will appear. This tool allows you to create a flow-chart like view of the design you have chosen to Place & Route. You can use the middle mouse button to expand the design hierarchy down to its leaf (most primitive) nodes.
Select (with the left mouse button) the top node in the hierarchy (the PR_adder_top box). The box should become red to indicate it is selected.
Select Hierarchy->Generate Physical Hierarchy. This command runs through the entire hierarchy of the design, looking for primitive cells (in this case all the primitive cells are CMOS4S standard cells). A new autoLayout cellview will be created if the command completes successfully.
Edit the autoLayout cellview just created. You'll see all the cells used in your design packed together, around the lower left corner of a placement rectangle.
From the menubar on the autoLayout cellview you are editing, Select Tools->Floorplan/P&R->Cell Ensemble. Several new menus will be added to the menu bar.
Select Floorplan->Reinitialize.... You can change various Place & Route options in the form that appears. Select OK. The arrangement of cells will change - the I/O cells will be moved to the top of the window, and the standard cells will be moved to the right side of the window. If you had any macro cells (custom layout cells) they would be placed to the left side of the window. In the center of the window you will see a box marked default. This is the default placment region, into which the standard cells will be placed. In more complex designs, it is sometimes necessary to create more than one placement region, or to modify properties of placement regions. In simple designs like this one, the defaults generally suffice.
Select Place->Automatic.... A number of Place & Route options can be set here or in the Initial or Improve forms invoked from this form. Select OK. All the standard cells and I/O pads should be placed when this command completes.
Select Place->IO Commands->Add Corners.... In the popup form which appears select cmos4s as the Glue Cell Library Name. The name of the corner cell should be set to corner1.w. Select OK. In each corner of the central I/O placement box, a corner1.w cell will appear.
Select Place->IO Commands->Improve. (This seems to be optional, and sometimes actually seems to have detrimental effects).
Select Place->IO Commands->Justify. You can experiment with values for IO to Core Spacing and IO to IO Spacing. The second is sometimes necessary to prevent adjacent I/O cells from overlapping. After executing this command, the I/O cells will be spread and justified. Note that there is a lot of wasted area in this layout. Luckily it is just an example, and no-one would ever actually have this chip fabricated.
When using the CMOS4S wide I/O pads, you need to run the CMOS4S->CMOS4S Functions->CMOS4SflipWideIO() from the CIW.
In general, you need to modify some of the properties of specific nets, particularly properties like routing width or routing priority. To modify the properties of a net, select the Route->Modify Net->Modify Net Properties... item. In the form that appears, enter the name of the net to modify, and click on the tag for each property you wish to modify. For this example, you will modify the nets/net properties as in the following table:
```
    Net Names     Edit Net Priority    Edit Net Width     Edit Net Type
    -------------------------------------------------------------------
    gnd!                115                 5.0             ground
    gndring!            115                75.0             ground
    vdd!                115                 5.0             supply
    vddring!            115                75.0             supply
```
Select Route->Sequencer.... In the popup form, set the Global Route to on. Select the global button to bring up the options form for global routing, and set the Use Stub Routing on. Stub routing is a special form of routing which allows adjacent cells to be connected by direct wires, rather than forcing the wiring into the routing channels in all cases. Select OK in the global route options form, then OK in the Route->Sequencer... form. You will probably see lots of warnings - just ignore them.
You can view the routing wires by selecting Design->Options->Display... (or by using the 'e' short keyboard command) and setting the Display Levels item To field to some number > 0.
To complete the layout the abstract cellviews used by the Place & Route system must be converted to their layout counterparts. Use the Hierarchy Browser (HB) to do this:
- unselect the top level of the design in the HB.
- expand the top level of the design in the HB window.
- select all the leaf nodes in the HB.
- select Utilities->Cross Select. All the cells in the autoLayout window should become highlighted.
- You may need to manually select the corner cells by Shift-clicking on them with the left mouse button.
- in the autoLayout window, select Floorplan->Replace View.... In the popup form select layout as the To View Name item. Each selected cell will be replaced with its layout cellview.
It is possible to manually select the cells you want to convert. Make sure the Instance item in the OSW is highlighted, and all other boxes are off. Area select (or individually select) all cells you wish to convert, and use Floorplan->Replace View....

At this point you should run Design->Save As to save the design as a layout cellview.

You are done.