Students working with Steve Wilton:

Graduate Students:

Nikhil Ghanathe: FPGA Architecture and CAD
Andrew-David Gunter: FPGA Architecture and CAD
Kahlan Gibson: FPGA Clocking
Daniel Holanda Noronha Machine Learning CAD
Jose Pinilla Gomez: Mapping algorithms for Quantum Computers
Esther Roorda: FPGA Architectures and CAD
Bahar Salehpour: FPGA CAD for Machine Learning

Former Graduate Students and Post-Docs:

Al-Shahna Jamal: MASc, August 2018

Thesis title: An FPGA overlay architecture supporting software-like compile times during on-chip debug of high-level synthesis designs
Now with Microsoft (Brainwave)

Fatemeh Eslami: PhD, August 2018

Thesis title: Rapid Instrumentation for Debug and Verification of Circuits on FPGAs
Now with Aupera Technologies

Pavan Bussa Kumar: MASc, August 2017

Thesis title: Accelerating in-system debug of high-level synthesis generated circuits on field-programmable gate arrays using incremental compilation techniques

Motahareh (Sarah) Mashayekhi: MASc, February 2017

Thesis Title: A Stochastic RTL Circuit Generator for FPGA Architecture and CAD Evaluation
Now with Google

Dr. Jeff Goeders: PhD, September 2016

Thesis Title: Techniques for Enabling In-System Observation-based Debug of High-Level Synthesis Circuits on FPGAs
Now an Assistant Professor at Brigham Young University

Jose Pinilla, MASc, September 2016

Thesis Title: Source-Level Instrumentation for In-System Debug of High-Level Synthesis Designs for FPGA
Now a PhD student in this group

Dr. Rehan Ahmed: PhD, June 2015

Thesis Title: Towards High-Level Leakage Power Reduction Techniques for FPGAs
Now at Ixia

Dr. Aaron Severance: PhD, March 2015

Thesis Title: Broadening the Applicability of FPGA-based Soft Vector Processors
Now at Vectorblox

Dr. Assem Bsoul: PhD, Sept 2014

Thesis Title: FPGA Architecture and CAD Algorithms with Dynamic Power Gating Support
Now at Microsoft

Dr. Eddie Hung: PhD, June 2013

Thesis Title: Harnessing FPGAs for Rapid Circuit Debug
Now at Verific

Stuart Dueck: MASc, June 2013

Thesis Title: A Power Evaluation Framework for FPGA Applications and CAD Experimentation
Now at Nvidia

Jeffrey Goeders: MASc, October 2012

Thesis Title: Power Estimation for Diverse Field Programmable Gate Array Architectures
Now an Assistant Professor at Brigham Young University

Dr. Joydip Das: PhD, October 2012

Thesis Title: Analytical Models for Accelerating FPGA Architecture Development
Now at Samsung

Kyle Balston: MASc, October 2012

Thesis Title: FPGA Emulation for Critical-Path Coverage Analysis
Now with Intel

Dr. Scott Chin: PhD, July 2011

Thesis Title: Improving the Run-Time and Memory Scalability of FPGA CAD Algorithms
Now with Qualcomm

Dr. Usman Ahmed: PhD, April 2011

Thesis Title: Impact of Custom Interconnect Masks on Cost and Performance of Structured ASICs
Co-supervised with Guy Lemieux
Now with Intel

Brad Quinton: Post-Doc

Now with Qualcomm

Dr. Sohaib Majzoub: Ph.D. August 2010.

Thesis Title: Energy Optimization for Many-Core Platforms under Process, Voltage and Temperature Variations
Now an Assistant Professor at University of Sharjah

Dr. Dipanjan Sengupta: Ph.D. July 2010.

Thesis Title: Low Power System-on-Chip Design using Voltage Islands: from Application to Floorplan [pdf]
Now at AMD

Andrew Lam, M.A.Sc. Feb 2010.

Thesis Title: An Analytical Model of FPGA Logic Resource Utilization for Architecture Development [abstract] [pdf]
Now with Frasier Health Authority

Marcel Gort, M.A.Sc. Aug 2008.

Thesis Title: Practical Considerations for Post-Silicon Debug using BackSpace [abstract] [pdf]
Now at Intel

Cindy Mark, M.A.Sc. November 2008.

Thesis Title: A System-Level Synthetic Circuit Generator for FPGA Architectural Analysis [abstract] [pdf]
Now with Intel

Dr. Brad Quinton, Ph.D., October 2008.

Thesis Title: A Reconfigurable Post-Silicon Debug Infrastructure for Systems-on-Chip [abstract] [pdf]
Now with Qualcomm

Dr. Alastair Smith, Post-Doc, October 2008.

Now at PA Consulting

Dr. Julien Lamoureux, Ph.D., September 2007

Thesis Title: Modeling and Reduction of Dynamic Power in Field-Programmable Gate Arrays [abstract] [pdf]

Nathalie Chan King Choy, M.A.Sc., October 2006

Thesis Title: Activity-based Power Estimation and Characterization of DSP and Multiplier Blocks in FPGAs [abstract] [pdf]
Now at Xilinx

Scott Chin: M.A.Sc., August 2006

Thesis Title: Power Implications of Implementing Logic using FPGA Embedded Memory Blocks
Now with Qualcomm

Zion Kwok: M.A.Sc., April 2005

Thesis Title: Register File Architecture Optimization in a Coarse-Grained Reconfigurable Array
Now with Intel

Andy Yan: M.A.Sc., January 2005

Thesis Title: Product-Term Based Synthesizable Embedded Programmable Logic Cores [abstract] [pdf] [slides]
Now with Microsoft

James Wu, M.A.Sc., September 2004

Thesis Title: Implementation Considerations for "Soft" Embedded Programmable Logic Cores [abstract] [pdf]
Now with Microsemi

Noha Kafafi: M.A.Sc. Nov 2003.

Thesis Title: Architectures and Algorithms for Embedded Synthesizable Programmable Logic Cores [slides]
Now with Teradici

Julien Lamoureux: M.A.Sc. June 2003.

Thesis Title: On the Interaction Between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays [abstract] [pdf]

Peter Hallschmid: M.A.Sc. June 2003.

Thesis Title: Detailed Routing Architectures for Embedded Programmable IP Cores
Now CEO of Blackcomb Design Automation

Danna Cao: M.Eng, May 2003.

Project Title: FPGA Routing Circuitry
Now with Microsoft

Kara Poon: M.A.Sc. August 2002.

Thesis Title: Power Estimation for Field-Programmable Gate Arrays [abstract] [pdf] [code].
Now at Efinix

Maria Lei: M.Eng. August 2002.

Project Title: Bluetooth Qualification
Now with Microsoft

Tony Wong: M.A.Sc. May 2002.

Thesis Title: Non-Rectangular Embedded Programmable Logic Cores [abstract] [pdf]
Now at NDCHealth.

Steve Oldridge: M.A.Sc. April 2002.

Thesis Title: A Novel FPGA Architecture Supporting Wide Shallow Memories [abstract] [pdf]

Ernie Lin, M.A.Sc. September 2001.

Thesis Title: Product Term Mode Embedded Memory Arrays: Algorithms and Architectures [abstract] [pdf]
Now at Microsemi

Imran Masud, M.A.Sc. December 1999.

Thesis Title: ``FPGA Routing Structures: A Novel Switch Block and Depopulated Interconnect Matrix Architecture'' [abstract] [pdf]

If you wish to work in this group, please read this.

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