STEVE
WILTONÕS PUBLICATIONS:
1. REFEREED
PUBLICATIONS
(a) Journals:
- E. Hung, S.J.E. Wilton, ÒIncremental Trace-Buffer
Insertion for FPGA DebugÓ, to appear in IEEE Transactions on Very-Large
Scale (VLSI) Integration, accepted March 2013.
- J. Das, S. Wilton, ÒTowards Development of An
Analytical Model Relating FPGA Architecture Parameters to RoutabilityÓ, ACM
Trans. on Reconfigurable Tech. and Systems, accepted Jan 2013.
- E. Hung, S. Wilton, ÒScalable Signal Selection
for Post-Silicon DebugÓ, to appear in IEEE Transactions on VLSI, accepted
May 2012.
- K. Balston, M. Karimibiuki, A. Hu, A. Ivanov,
S.J.E. Wilton, ÒPost-Silicon Code Coverage for Multiprocessor
System-on-Chip DesignsÓ, IEEE Transactions on Computers, Vol. 62, Issue 2,
Feb. 2013, pp. 242-246.
- M. Gort, F.M. De Paula, J.W. Kuan, T.M. Aamodt,
A.J. Hu, S.J.E. Wilton, J. Yang, ÒFormal-Analysis-Based Trace Computation
for Post-Silicon DebugÓ, IEEE Transactions on Very-Large Scale (VLSI) Integration,
vol. 20, no. 11, Nov 2012, pp. 1997-2010.
- C. Mark, S. Chin, L. Shannon, S.J.E. Wilton, Ó
Hierarchical Benchmark Circuit Generation for FPGA Architecture
EvaluationÓ, ACM Transactions on Embedded Computing Systems, vol. 11,
issue S2, Aug 2012, article No. 42.
- C.H. Ho, A.M. Smith, W. Luk, P.H.W. Leong, S.J.E.
Wilton, "Optimizing Floating Point Units in Hybrid FPGAs", IEEE
Transactions on Very-Large Scale (VLSI) Integration Systems, vol. 20, no.
7, July 2012, pp. 1295-1303.
- D. Sengupta, A. Veneris, S. Wilton, A. Ivanov,
ÒMulti-Objective Voltage Island Floorplanning using Sequence Pair
RepresentationÓ, Sustainable Computing: Informatics and Systems, Elsevier,
Volume 2, Issue 2, June 2012, Pages 58–70.
- U. Ahmed, G. Lemieux, S. Wilton,
"Performance and Cost Trade-offs in Metal-Programmable Structured
ASICs (MPSAs)", IEEE Transactions on Very-Large Scale (VLSI)
Integration, vol. 19, no. 12, Dec 2011, pp. 2195-2208.
- J. Das, A. Lam, S. Wilton, P. Leong, W. Luk, ÒAn
Analytical Model Relating FPGA Architecture to Logic Density and DepthÓ,
IEEE Transactions on Very-Large Scale (VLSI) Integration, vol. 19, no. 12,
Dec 2011, pp. 2229-2242.
- S. Majzoub, R. Saleh, S. Wilton, R. Ward,
"Energy Optimization for Many-Core Platforms: Communication and PVT
Aware Voltage-Island Formation and Voltage Selection Algorithm", IEEE
Transcations on Computer-Aided Design, vol. 29, Issue 5, May 2010, pp.
816-829.
- C.H. Ho, C.W. Yu, P. Leong, W. Luk, S.J.E.
Wilton, ÒFloating Point FPGA: Architecture and ModellingÓ, IEEE Trans. on
Very-Large Scale (VLSI) Integration Systems, vol. 17, no. 12, pp.
1709-1718, December 2009.
- B.R. Quinton, S.J.E. Wilton, ÒProgrammable Logic
Core Enhancements for High Speed On-Chip InterfacesÓ, IEEE Transactions on
Very-Large Scale (VLSI) Integration Systems, vol. 17, no. 7, Sept 2009,
pp. 1334-1339.
-
S. Chin, S.J.E. Wilton, ÒStatic
and Dynamic Memory Footprint Reduction for FPGA Routing AlgorithmsÓ, ACM
Transactions on Reconfigurable Technology and Systems, vol. 1, issue 4,
January 2009, pp. 18.1-18.20.
- C.W. Yu, J. Lamoureux, S.J.E. Wilton, P.H.W.
Leong and W. Luk, ÒThe Coarse-Grained/Fine-Grained Logic Interface in
FPGAs with Embedded Floating-Point Arithmetic UnitsÓ, International
Journal of Reconfigurable Computing, vol. 2008, Article ID 736203, 10
pages.
- J. Lamoureux, G. Lemieux, S.J.E. Wilton, ÒGlitchLess:
Dynamic Power Minimization in FPGAs through Edge Alignment and Glitch
FilteringÓ, IEEE Transactions on IEEE Transactions on Very-Large Scale
Integration (VLSI), vol. 16, no. 11, Nov. 2008, pp. 1521-1534.
- J. Lamoureux, S.J.E. Wilton, ÒOn the Interaction
between Power and Flexibility of FPGA Clock NetworksÓ, ACM Transactions on
Reconfigurable Technology and Systems, vol. 1, no. 3, Sept 2008, pp. 13.1-13.33.
- S. Chin, C. Lee, S.J.E. Wilton, ÒOn the Power
Dissipation of Embedded Memory Blocks Used to Implement Logic in
Field-Programmable Gate ArraysÓ,
International Journal of Reconfigurable Computing, vol 2008, no. 1,
13 pages.
- B.R. Quinton, M.R. Greenstreet, S.J.E. Wilton,
ÒPractical Asynchronous Interconnect Network DesignÓ, IEEE Transactions on Very-Large
Scale Integration (VLSI), vol. 16, no. 5, May 2008, pp 579-588.
-
S.J.E. Wilton, B. Quinton,
C.H. Ho, P.H.W. Leong, W. Luk, ÒA Synthesizable Datapath-Oriented Embedded
FPGA Fabric for Silicon Debug ApplicationsÓ, ACM Transactions on Reconfigurable Technology and
Systems, vol. 1, no. 1, March 2008, pp 7.1-7.25.
- R. Saleh, S. Wilton, S. Mirabbasi, A. Hu, M.
Greenstreet, , G. Lemieux, P. Pande, C. Grecu, A. Ivanov, ÒSystem-on-Chip:
Reuse and IntegrationÓ, Proceedings of the IEEE, Vol. 94, No. 6, June
2006, pp. 1050-1069.
- A. Yan, S.J.E. Wilton, "Product-Term Based
Synthesis Embedded Programmable Logic Cores", IEEE Transactions on
Very-Large Scale Integration (VLSI) Systems, Vol. 14, Issue 5, May 2006,
pp. 474-488.
- P. Hallschmid and S.J.E. Wilton, " Routing Architecture Optimizations for
High-Density Embedded Programmable IP Cores", IEEE Transactions on
Very-Large Scale Integration (VLSI) Systems, Vol. 13, Issue 11, November
2005, pp. 1320-1324.
-
J. Lamoureux and S.J.E.
Wilton, "On the Interaction Between Power-Aware Computer-Aided Design
Algorithms for Field-Programmable Gate Arrays", Journal of Low Power
Electronics, Vol. 1, No. 2, August 2005, pp. 119-132.
- S.W. Oldridge and S.J.E. Wilton, ÒA Novel FPGA
Architecture Supporting Wide, Shallow MemoriesÓ, IEEE Transactions on Very-Large
Scale Integration (VLSI) Systems, Vol. 13, Issue 6, June 2005, pp. 758-762
-
K.K.W. Poon, S.J.E.
Wilton, A. Yan, ÒA Detailed Power Model for Field Programmable Gate
ArraysÓ, ACM Transactions on
Design Automation of Electronic Systems, Vol. 10, Issue 2, April 2005, pp.
279-302.
- T.J. Todman, G.A. Constantinides, S.J.E. Wilton,
O. Mencer, W. Luk and P.Y.K. Cheung, ÒReconfigurable Computing:
Architectures and Design MethodsÓ, IEE Proceedings: Computers &
Digital Techniques, Vol. 152,
No. 2, March 2005, pp. 193-208.
-
S.J.E. Wilton, N. Kafafi,
J. Wu, K. Bozman, V. AkenÕOva, R. Saleh, ÒDesign Considerations for Soft
Embedded Programmable Logic CoresÓ, IEEE Journal of Solid-State Circuits,
Vol. 40, No. 2, February 2005, pp. 485-497 .
(b) Conference
Proceedings:
- E. Hung, F. Eslami, S.J.E. Wilton, ÒEscaping the
Academic Sandbox: Realizing VPR Circuits on Xilinx DevicesÓ, to appear in
IEEE International Symposium on Field-Programmable Custom Computing
Machines, April 2013.
- E. Hung, S.J.E. Wilton, ÒTowards Simulator-like
Visibility for FPGAs: Virtual Overlay Networks for Trace BuffersÓ, ACM/SIGDA
International Symposium on Field Programmable Gate Arrays, Feb. 2013, pp.
19-28.
- S.J.E. Wilton, B.R. Quinton, E. Hung, ÒRapid
RTL-based signal ranking for FPGA prototypingÓ, IntÕl Conf. on
Field-Programmable Technology, Dec 2012, pp. 1-7.
- A.A.M. Bsoul, S.J.E. Wilton. ÒAn FPGA with
Power-Gated Switch BlocksÓ, IntÕl Conf. on Field-Programmable Technology,
Dec 2012, pp. 87-94.
- J. Goeders, S.J.E. Wilton, ÒVersaPower: Power
Estimation for Diverse FPGA ArchitecturesÓ, IntÕl Conf. on
Field-Programmable Technology, Dec 2012, pp. 229-234 (poster
presentation).
- E. Hung, S.J.E. Wilton, ÒLimitations of
incremental signal-tracing for FPGA DebugÓ, IntÕl Conf. on
Field-Programmable Logic, Aug 2012, pp. 49-56.
- A.A.M. Bsoul, S.J.E. Wilton, ÒA Configurable
Architecture to Limit Wakeup Current in Dynamically-Controlled Power-Gated
FPGAs,Ó ACM/SIGDA International Symposium on Field Programmable Gate
Arrays, Feb. 2012, pp. 245-254.
- J. Goeders, G. Lemieux, S.J.E. Wilton, "Deterministic
Timing-Driven Parallel Placement by Simulated Annealing using Half-box
Window Decomposition", International
Conference on Reconfigurable Computing and FPGAs, Dec. 2011, pp. 41-48.
- J. Das, S.J.E. Wilton, ÒAccelerated FPGA
Architecture Design: Capabilities and Limitations of Analytical ModelsÓ,
International Conference on Field-Programmable Technology, December 2011,
pp. 1-8.
- E. Hung, S.J.E. Wilton, ÒSpeculative Debug
Insertion For FPGAsÓ, in International Conference on Field-Programmable
Logic, Sept. 2011, pp. 524-531.
- Dipanjan Sengupta, A. Veneris, S. Wilton, A.
Ivanov, R. Saleh, ÒSequence Pair
Based Voltage Island FloorplanningÓ, International Green Computing
Conference, August 2011.
- E. Hung, S.J.E. Wilton, ÒOn Evaluating Signal
Selection Algorithms for Post-Silicon DebugÓ, International Symposium on
Quality Electronic Design, Mar. 2011, pp. 290-296.
- S.Y.L Chin, S.J.E. Wilton, ÒTowards Scalable FPGA
CAD Through ArchitectureÓ, ACM International Symposium on
Field-Programmable Gate Arrays, Feb. 2011, pp. 143-152.
- J. Das, S.J.E. Wilton, "An Analytical Model
Relating FPGA Architecture Parameters to RoutabilityÓ, ACM International
Symposium on Field-Programmable Gate Arrays, Feb 2011 (short paper), pp.
181-184.
- A.A.M. Bsoul, S.J.E. Wilton, ÒAn FPGA
Architecture Supporting Dynamically Controlled Power Gating,Ó
International Conference on Field-Programmable Technology (FPT'10),
Beijing, China, Dec. 2010, pp. 1-8.
- J. Ho, S.J.E. Wilton, T. Aamodt, ÒAccelerating
Trace Computation in Post-Silicon DebugÓ, in International Symposium on
Quality Electronic Design, March 2010, pp. 244-249. (poster presentation)
- U. Ahmed, G. Lemieux, S.J.E. Wilton, ÒThe Impact
of Interconnect Architecture on Via-Programmed Structured ASICs (VPSAs)Ó,
ACM International Symposium on Field-Programmable Gate Arrays, Feb 2010,
pp. 263-272.
- A. Smith, G. Constantinides, S.J.E. Wilton,
P.Y.K. Cheung, ÒConcurrently Optimizing FPGA Architecture Parameters and
Transistor Sizing: Implications for FPGA DesignÓ, International Conference
on Field-Programmable Technology,. Sydney, Australia, Dec 2009, pp. 54-61.
- E. Hung, H. Yu, T. Chau, P.H.W. Leong, S.J.E.
Wilton, ÒA Detailed Delay Path Model for FPGAsÓ, International Conference
on Field-Programmable Technology,. Sydney, Australia, Dec 2009, pp.
96-103.
- G. Smecher, S. Wilton, G. Lemieux, ÒSelf-Hosted
Placement for Massively Parallel Processor ArraysÒ, International
Conference on Field-Programmable Technology,. Sydney, Australia, Dec 2009,
pp. 159-166.
- D. Chiu, G. Lemieux, S. Wilton,
ÒCongestion-Driven Regional Re-Clustering for Low Cost FPGAsÓ,
International Conference on Field-Programmable Technology,. Sydney,
Australia, Dec 2009, pp. 167-174.
- U. Ahmed, G. Lemieux, S. Wilton, ÒArea, Delay,
Power, and Cost Trends for Metal-Programmable Structured ASICS (MPSAs)Ó,
International Conference on Field-Programmable Technology,. Sydney,
Australia, Dec 2009. pp. 278-284 (poster presentation)
- P. Jamieson, W. Luk, G. Constantinides, S.
Wilton, ÒAn Energy and Power Consumption Analysis of FPGA Routing
ArchitecturesÓ, International Conference on Field-Programmable
Technology,. Sydney, Australia, Dec 2009, pp. 324-327. (poster
presentation)
- C.W. Yu, W. Luk, S.J.E. Wilton, P.H.W. Leong,
ÒRouting Optimization for Hybrid FPGAsÓ, International Conference on
Field-Programmable Technology,. Sydney, Australia, Dec 2009, pp. 419-422.
(poster presentation)
- S. Majzoub, R. Saleh, S. Wilton, R. Ward, ÒSimultaneous
PVT-Tolerant Voltage-Island Formation and Core Placement for Thousand-Core
PlatformsÓ, International Symposium on System-on-Chip, October 2009, pp.
1-4.
- X. Meng, R. Saleh, S. Wilton, ÒCharge-Borrowing
Decap: A Novel Circuit for Removal of Local Supply Noise ViolationsÓ, IEEE
Custom Integrated Circuits Conference, September 2009, pp. 25-28.
- S. Majzoub, R. Saleh, S. Wilton, R. Ward,
ÒRemoval-Cost Method: An Efficient Voltage Selection Algorithm for
Multi-Core Platforms under PVTÓ, IEEE International SoC Conference, August
2009, pp. 357-360.
- S. Chin, S.J.E. Wilton, ÒAn Analytical Model
Relating FPGA Architecture and Place and Route RuntimeÓ, International
Conference on Field-Programmable Logic, August 2009, pp.146-153.
- J. Das, S.J.E. Wilton, W. Luk, P.H.W. Leong, ÒModeling
Post-Techmapping and Post-Clustering FPGA Circuit DepthÓ, International
Conference on Field-Programmable Logic, August 2009, pp. 205-211.
- A.M. Smith, J. Das, S.J.E. Wilton,
"Wirelength Modeling for Homogeneous and Heterogeneous FPGA Architectural
Development", ACM International Symposium on Field-Programmable Gate
Arrays, Monterey, CA, Feb 2009, pp. 181-190.
- C.Yu, A. Smith, W. Luk, P. Leong, S.J.E. Wilton,
ÒOptimizing Coarse-Grained Units in Floating Point Hybrid FPGAsÓ, in International
Conference on Field-Programmable Technology, Taipei, Taiwan, December
2008, pp. 57-64.
- C. Mark, A. Shui, S.J.E. Wilton, ÒA System-Level
Stochastic Circuit Generator for FPGA Architecture EvaluationÓ, in
International Conference on Field-Programmable Technology, Taipei, Taiwan,
December 2008, pp. 25-32.
- F.M. De Paula, M. Gort, A.J. Hu, S.J.E. Wilton,
"Backspace: Formal Analysis for Post-Silicon Debug", in Formal
Methods in Computer-Aided Design, Portland, OR, November 2008, pp. 35-44.
- A. Lam, S.J.E. Wilton, P. Leong, W. Luk, ÒAn
Analytical Model Describing the Relationship between Logic Architecture
and FPGA DensityÓ, in the International Conference on Field-Programmable
Logic and Applications, September 2008, pp. 221-226.
- C.H. Ho, P. Leong, W. Luk, S.J.E. Wilton, ÒRapid
Estimation of Power Consumption for Hybrid FPGAsÓ, in the International
Conference on Field-Programmable Logic and Applications, September 2008,
pp. 237-227-232. Stamatis Vassiliadis Outstanding Paper
Award
- C.W. Yu, J. Lamoureux, S. Wilton, P.H.W. Leong,
W. Luk, "The Coarse-Grained/Fine-Grained Logic Interface in FPGAs
with Embedded Floating-Point Arithmetic Units", Southern Programmable
Logic Conference, Bariloche, Argentina, March 2008, pp. 63-68. Best Student Paper Award.
-
S. Chin, S.J.E. Wilton, ÒMemory
Footprint Reduction For FPGA Routing AlgorithmsÓ, in the IEEE
International Conference on Field-Programmable Technology, Kitakyushu,
Japan, December 2007, pp. 1-8. Best
Paper Award
- B. Quinton, S.J.E. Wilton, "Embedded
Programmable Logic Core Enhancements for System Bus Interfaces", in
the International Conference on Field-Programmable Logic and Applications,
Amsterdam, August 2007.
- C.H. Ho, C.W. Yu, P.H.W. Leong, W. Luk, S.J.E.
Wilton, "Domain-Specific Hybrid FPGA: Architecture and Floating Point
Applications", in the International Conference on Field-Programmable
Logic and Applications, Amsterdam, August 2007. Stamatis Vassiliadis Outstanding Paper Award
- J. Lamoureux, S.J.E. Wilton, ÒClock-Aware
Placement for FPGAsÓ, International Conference on Field-Programmable Logic
and Applications, Amsterdam, August 2007.
- S.J.E. Wilton, C.H. Ho, W. Luk, P. Leong, B.
Quinton ÒA Synthesizable
Datapath-Oriented Embedded FPGA FabricÓ, in the ACM/SIGDA International
Symposium on Field-Programmable Gate Arrays, Monterey, California, Feb
2007, pp. 33-41.
- J. Lamoureux, G. Lemieux, S.J.E. Wilton, ÒGlitchLess:
An Active Glitch Minimization Technique for FPGAsÓ, in the ACM/SIGDA
International Symposium on Field-Programmable Gate Arrays, Monterey,
California, Feb 2007, pp. 156-165.
- N. Chan King Choy, S.J.E. Wilton, ÒActivity-based
Power Estimation and Characterization of DSP and Multiplier Blocks in
FPGAsÓ, in the IEEE International Conference on Field-Programmable
Technology, to be held in Bangkok, Thailand, Dec 2006. (refereed poster presentation)
- J. Lamoureux, S.J.E. Wilton, ÒActivity Estimation
for Field-Programmable Gate ArraysÓ, in the International Conference on
Field-Programmable Logic and Applications, Madrid, Spain, August 2006, pp.
87-94
- S. Chin, C. Lee, S.J.E. Wilton, ÒPower
Implications of Implementing Logic in FPGA Embedded Memory ArraysÓ, in the
International Conference on Field-Programmable Logic and Applications,
Madrid, Spain, August 2006, pp. 95-102. Altera Award on
FPGA Architectures
- C.H. Ho, P. Leong, W. Luk, S. Wilton and S.
Lopez-Buedo, ÒVirtual Embedded Blocks: A Methodology for Evaluating
Embedded Elements in FPGAsÓ, in the IEEE Symposium on Field-Programmable
Custom Computing Machines, Napa, California, April 2006.
- J. Lamoureux, S.J.E. Wilton, ÒFPGA Clock Network
Architecture: Flexibility vs. Area and PowerÓ, in ACM/SIGDA International
Symposium on Field-Programmable Gate Arrays, Monterey, California, Feb
2006, pp. 101-108.
- B.R. Quinton and S.J.E. Wilton,
"Post-Silicon Debug Using Programmable Logic Cores", in the IEEE International
Conference on Field-Programmable Technology, Singapore, December 2005, pp.
241-250.
- C.T. Chow, L.S.M. Tsui, P. Leong, W. Luk, S.J.E.
Wilton, "Dynamic Voltage Scaling for Commercial FPGAs", in the
IEEE International Conference on Field-Programmable Technology, Singapore,
December 2005, pp. 173-180. Best
Paper Award
- B.R. Quinton, M. Greenstreet, S.J.E. Wilton,
" Asynchronous IC Interconnect
Network Design and Implementation Using a Standard ASIC Flow", in the
IEEE International Conference on Computer Design, October 2005, pp.
267-274.
- B.R. Quinton and S.J.E. Wilton, ÒConcentrator
Access Networks for Programmable Logic Cores on SoCsÓ in IEEE
International Symposium on Circuits and Systems, May 2005, pp. 45-48.
- Z. Kwok and S.J.E. Wilton, "Register File
Architecture Optimization in a Coarse-Grained Reconfigurable
Architecture", in IEEE Symposium on Field-Programmable Custom
Computing Machines, Napa, California, April 2005.
- T. Wong, S.J.E. Wilton, ÒPlacement and Routing
for Non-Rectangular Embedded Programmable Logic Cores in SoC DesignÓ, in
the IEEE International Conference on Field-Programmable Technology,
Brisbane, Australia, December 2004, pp. 65-72.
- S.J.E. Wilton, N. Kafafi, B. Mei, S. Vernalde,
ÒInterconnect Architectures for Modulo-Scheduled Coarse-Grained
Reconfigurable ArraysÓ, in the IEEE International Conference on
Field-Programmable Technology, Brisbane, Australia, December 2004, pp.
33-40.
- Andy Yan, S.J.E. Wilton, ÒSequential
Synthesizable Embedded Programmable Logic Cores for System-on-ChipÓ, in
the IEEE Custom Integrated Circuits Conference, Orlando, FL, October 2004,
pp. 435-438.
- S.J.E. Wilton, S-S. Ang, W. Luk, ÒThe Impact of
Pipelining on Energy per Operation in Field-Programmable Gate ArraysÓ, in
the International Conference on Field-Programmable Logic and Applications,
Antwerp, Belgium, August 2004. Included in Lecture Notes in Computer
Science 3203, Springer-Verlag, pp. 719-728. Michal Servit Best
Paper Award.
- S.J.E. Wilton, C.W. Jones, J. Lamoureux ÒAn
Embedded Flexible Content-Addressable Memory Core for Inclusion in a
Field-Programmable Gate ArrayÓ, in the IEEE International Symposium on
Circuits and Systems, Vancouver, B.C., May 2004, Vol II, pp. 885-888. (refereed poster presentation)
58. S.W. Oldridge, S.J.E. Wilton, ÒPlacement and Routing
for FPGA Architectures Containing Wide Shallow MemoriesÓ, in the IEEE International
Conference on Field-Programmable Technology, Tokyo, Japan, December 2003, pp. 154-161.
- Andy Yan, S.J.E. Wilton, ÒProduct-Term Based
Synthesizable Embedded
Programmable Logic CoresÓ, to appear in the IEEE International
Conference on Field-Programmable Technology, Tokyo, Japan, December
2003, pp. 162-169. Best Paper Award
60.
J. Lamoureux, S.J.E. Wilton,
ÒOn the Interaction between Power-Aware FPGA CAD AlgorithmsÓ, in the IEEE
International Conference on Computer-Aided Design, San Jose, CA, November 2003, pp 701-708.
61. J.C.H. Wu, V. AkenÕOva, S.J.E. Wilton, R. Saleh, ÒSoC Implementation Issues for
Synthesizable Embedded Programmable Logic CoresÓ, in the IEEE Custom Integrated
Circuits Conference, San Jose,
California, September 2003, pp. 45-48.
62.
N. Kafafi, K. Bozman, S.J.E.
Wilton, ÒArchitectures and Algorithms for Synthesizable Embedded Programmable
Logic CoresÓ, to appear in the ACM International Symposium on
Field-Programmable Gate Arrays, Monterey, California, February 2003, pp. 1-9.
- S.J.E. Wilton, ÒImplementing Logic in FPGA Memory
Arrays: Heterogeneous Memory ArchitecturesÓ, in the IEEE International
Conference on Field-Programmable Technology, Hong Kong, December 2002, pp.
142-149.
64.
K.K.W. Poon, A. Yan, S.J.E.
Wilton, ÒA Flexible Power Model for FPGAsÓ, in the International Conference on Field-Programmable
Logic and Applications, Montpellier, France, September 2002. Included in
Lecture Notes in Computer Science 2438, Springer-Verlag, pp. 48-58.
- E. Lin, S.J.E. Wilton, ÒThe Architecture of Dual-Mode
FPGA Embedded Systems BlocksÓ, in the IEEE Custom Integrated Circuits
Conference, Orlando, Florida, May 2002, pp. 63-66.
66. Andy Yan, R. Cheng, S.J.E. Wilton, ÒOn the Sensitivity
of FPGA Architectural Conclusions for Experimental Assumptions, Tools, and
TechniquesÓ, in the ACM/SIGDA International Symposium on Field-Programmable
Gate Arrays, Monterey, California, Feb. 2002, pp. 147-156. One of top 20 papers in isFPGA from 1994-2012, awarded Feb 2012.
67. E. Lin, S.J.E. Wilton, ÒMacrocell Architectures for
Product Term Embedded Memory ArraysÓ, in the International Conference on
Field-Programmable Logic and Applications, August 2001, included in Lecture
Notes in Computer Science 2147, Springer-Verlag, pp. 48-58, Michal Servit Best Paper Award
68. S.J.E. Wilton, R. Saleh, ÒProgrammable Logic IP Cores
in SoC Design: Opportunities and ChallengesÓ, in the IEEE Custom Integrated
Circuits Conference, San Diego, California, May 2001, pp. 63-66.
69. S. Oldridge, S.J.E. Wilton, ÒA Novel FPGA Architecture
Supporting Wide Shallow MemoriesÓ, in the IEEE Custom Integrated Circuits
Conference, San Diego, California, May 2001, pp. 75-78.
70. S.J.E. Wilton, ÒA Crosstalk-Aware Timing-Driven Router
for FPGAsÓ, in the ACM International Symposium on Field-Programmable Gate
Arrays, Monterey, California, February 2001, pp. 21-28.
71. P. Hallschmid, S.J.E. Wilton, ÒDetailed Routing
Architectures for Embedded Programmable Logic CoresÓ, in the ACM International
Symposium on Field-Programmable Gate Arrays, Monterey, California, February 2001, pp. 69-74.
72. W.W. Cheng, S.J.E. Wilton, B. Hamidzadeh, ÒFPGA
Implementation of a Prototype WDM On-Line SchedulerÓ, in the International
Conference on Field-Programmable Logic and Applications, Villach, Austria,
August 2000. Included in Lecture
Notes in Computer Science 1896, Springer-Verlag, pp. 773-776.
73. J.P. Clifford, S.J.E. Wilton, ÒArchitecture of
Cluster-Based FPGAs with MemoryÓ, in the IEEE Custom Integrated Circuits
Conference, Orlando, Florida, May 2000, pp. 131-134.
74. S.J.E. Wilton, ÒHeterogeneous Technology Mapping for
FPGAs with Dual-Port Embedded Memory Arrays,Ó in the ACM International
Conference on Field-Programmable Gate Arrays, Monterey, California, February
2000, pp. 67-74.
75. S.J.E. Wilton, ÒImplementing Logic in FPGA Embedded
Memory Arrays: Architectural Implications,Ó in the IEEE Custom Integrated
Circuits Conference, Santa Clara, California, May 1998, pp. 269-272.
-
S.J.E. Wilton, ÒSMAP:
Heterogeneous Technology Mapping for FPGAs with Embedded Memory Arrays,Ó
in ACM/SIGDA International Symposium on Field-Programmable Gate Arrays,
Monterey, California, February 1998, pp. 171-178.
- S.J.E. Wilton, J. Rose, Z.G. Vranesic,
ÒMemory-to-memory Connection Structures in FPGAs with Embedded Memory
Arrays,Ó in ACM/SIGDA International Symposium on Field-Programmable Gate
Arrays, Monterey, California, February 1997,pp.10-16.
- S.J.E. Wilton, J. Rose, Z.G. Vranesic,
ÒMemory/Logic Interconnect Flexibility in FPGAs with Large Embedded Memory
Arrays,Ó in IEEE Custom Integrated Circuits Conference, San Diego, California,
May 1996, pp. 144-147.
- S.J.E. Wilton, J. Rose, Z.G. Vranesic,
ÒArchitecture of Centralized Field-Configurable Memory,Ó in ACM/SIGDA
International Symposium on Field-Programmable Gate Arrays, Monterey,
California, February 1995, pp. 97-103.
- T. Ngai, J. Rose, S.J.E. Wilton, ÒAn
SRAM-Programmable Field-Configurable Memory,Ó in IEEE Custom Integrated
Circuits Conference, San Jose, California, May 1995, pp. 499-502.
- N.P. Jouppi, S.J.E. Wilton, ÒTradeoffs in
Two-Level On-Chip CachingÓ, in 21st Annual International Symposium on
Computer Architecture, Chicago, Illinois, April 1994, pp. 34-45.
- S.J.E. Wilton, Z.G. Vranesic, ÒArchitectural
Support for Block Transfers in a Shared Memory Multiprocessor,Ó in Fifth
IEEE Symposium on Parallel and Distributed Processing, Dallas, Texas,
December 1993, pp. 51-54.
83. G. Feygin, P. Chow, P.G. Gulak, J. Chappel, G. Goodes,
O. Hall, A. Sayes, S. Singh, M. Smith, S. Wilton, ÒA VLSI Implementation of a
Cascade Viterbi Decoder with Traceback,Ó in IEEE International Symposium on
Circuits and Systems, Chicago, Illinois, May 1993, pp. 1945-1948.
(c) Other
(Refereed Published Workshop Proceedings):
- E. Hung, S.J.E. Wilton, ÒTowards Simulator-Like
Visibility for FPGAsÓ, IEEE International Workshop on Silicon Debug and
Diagnosis, Nov 2012.
- K. Balston, A. Hu, S.J.E. Wilton, A. Nahir,
ÒEmulation in post-silicon validation: It's not just for functionality
anymoreÓ, IEEE IntÕl High Level Design Validation and Test Workshop, Nov.
2012, pp. 110-117.
- W.K.C. Ho, S.J.E. Wilton, ÒLogical-to-Physical
Memory Mapping for FPGAs with Dual-Port Embedded Arrays,Ó in International
Workshop on Field-Programmable Logic and Applications, Glasgow, U.K.,
September 1999.
Included in Lecture Notes in Computer Science 1673,
Springer-Verlag, pp. 111-123.
- M.I. Masud, S.J.E. Wilton, ÒA New Switch Block
for Segmented FPGAs,Ó in International Workshop on Field-Programmable
Logic and Applications, Glasgow, U.K., September 1999. Included in Lecture Notes in
Computer Science 1673, Springer-Verlag, pp. 274-281.
2. NON-REFEREED
PUBLICATIONS:
a)
Journals
- E. Charbon, F. Svelto , S.J.E. Wilton, ÒEditorial
(Introduction to the Special Issue on the 2002 Integrated Circuits Conference), in IEEE Journal
of Solid-State Circuits, Vol 38, No 3, March 2003, pp. 391-393.
- T.T. Rueger, S.J.E. Wilton, ÒEditorialÓ
(Introduction to Special Issue on the 2001 Custom Integrated Circuits
Conference), IEEE Journal of Solid-State Circuits, Vol. 37, No. 3, March
2002, pp. 267-269.
- T. Rissa, S.J.E. Wilton, ÒEditorial: Special
Issue on the 2005 International Conference on Field-Programmable Logic and
ApplicationsÓ, IEE Proceedings: Computers and Digital Techniques, to appear
June 2006.
b)
Conference Proceedings
- F.M. De Paula, M. Gort, A.J. Hu, S.J.E. Wilton,
"Backspace: Moving Towards Reality", in Microprocessor Test and
Verification Workshop, Austin, TX, December 2008 (invited non-refereed
paper).
- M. Gort, F. dePaula, A.J. Hu, S.J.E. Wilton, ÒFormal
Analysis to Support Post-Silicon DebugÓ, CMC Texpo Research Exhibition and
Competition, Ottawa, October 2008 (short paper accompanied by
demonstration, reviewed by abstract)
- K.K.W. Poon, S.J.E. Wilton, ÒSensitivity of FPGA Power EvaluationÓ,
in the IEEE International Conference on Field-Programmable Technology,
Hong Kong, December 2002.
(invited short paper – 2 pages).
- S.J.E. Wilton, ÒRecent Research in FPGA Embedded
Memory ArchitecturesÓ, in IEEE Pacific Rim Conference on Communications,
Computers, and Signal Processing, Victoria, B.C., August 1999, pp. 292-296
(refereed by abstract)
- E. Casas, E. Lin, S. Wilton, ÒAn Inexpensive
Laboratory for Teaching Digital Logic and Microcomputer Design,Ó in
Canadian Conference on Computer Engineering Education, Vancouver, B.C.,
June 1999. (refereed by
abstract)
- P.D. Kundarewich, S.J.E. Wilton, A.J. Hu, ÒA
CPLD-based RC4 Cracking System,Ó in Canadian Conference on Electrical and
Computer Engineering, Edmonton, Alberta, May 1999. (refereed by abstract)
(c) Other
(Workshops)
- S.J.E. Wilton, B.R. Quinton, E. Hung, ÒAddressing
FPGA Design, Verification, and Debug Productivity Challenges through
Increased AbstractionÓ, invited poster/abstract at Design Automation
Conference Work-in-Progress Session, San Francisco, CA, June 2012. Invited Feb 2012.
- M. Gort, S. Wilton, ÒBackspace: Formal Analysis
for Post Silicon DebugÓ, System and SoC Debug Integration and Applications
Workshop (co-located with Design Automation Conference), Anaheim,CA, June
2010.
- B.R. Quinton, A.M. Hughes, S.J.E. Wilton,
"Post-Silicon Debug of Complex Multi Clock and Power Domain
ICs", IEEE International Workshop on Silicon Debug and Diagnosis,
March 2010.
- B. Quinton, S.J.E. Wilton, ÒProgrammable Logic
Core Based Post-Silicon Debug For SoCsÓ, 4th IEEE Silicon Debug and Diagnosis Workshop,
Freiburg, Germany, May 2007. (refereed by abstract)
3. BOOK
Chapters
- Assem A.M. Bsoul, Stuart Dueck, and Steven J.E.
Wilton, ÒRuntime-Controlled Energy Reduction Techniques for FPGAs,Ó in
Green Communications: Theoretical Fundamentals, Algorithms and
Applications, eds. Jinsong Wu, Sundeep Rangan, and Honggang Zhang., CRC
Press, Sept. 2012.
- Andy Yan, R. Cheng, S.J.E. Wilton, ÒOn the
Sensitivity of FPGA Architectural Conclusions for Experimental Assumptions,
Tools, and TechniquesÓ, Highlights of the International Symposium on
Field-Programmable Gate Arrays, Feb 2012, pp 211-220 (reprint of
conference paper from 2002).
- S.J.E. Wilton, N. Chan King Choy, S.Y.L. Chin,
K.K.W. Poon, "Field-Programmable Gate Array Architectures", in
Handbook of Algorithms for Physical Automation, eds. Charles J. Alpert,
Dinesh P. Mehta, and Sachin S. Sapatnekar, Nov 2008, pp 941-956.
- T.J. Todman, G.A. Constantinides, S.J.E. Wilton,
O. Mencer, W. Luk and P.Y.K. Cheung, ``Reconfigurable Computing:
Architectures and Design Methods'' in Bashir M. Al-Hashimi, ed., System-on-Chip:
Next Generation Electronics, IEE Press, January 2006.
4. PATENTS
(not counting provisional patents)
- B. Quinton, A. Hughes, S.J.E. Wilton, ÒIn-Circuit
Data Collection Using Configurable Selection NetworksÓ, U.S. Patent
Application 13344427, Filed Jan 5, 2012.
- S.J.E Wilton, K. Bozman, N. Kafafi, J. Wu,
ÒMethod For Constructing An Integrated Circuit Device Having Fixed And
Programmable Logic Portions And Programmable Logic Architecture For Use
TherewithÓ, U.S. Patent 6,983,442, Issued Jan 6, 2006.
- A. Coppola, J. Stanley, S.J.E. Wilton,
"Interface scheme for connecting a fixed circuitry block to a
programmable logic core", U.S. Patent 6,747,479, Issued Jun 8,
2004.
- C.W. Jones, S.J.E. Wilton, ÒCascadable bus based crossbar
switching in a programmable logic deviceÓ, U.S. Patent 6,710,623, Issued March 23, 2004.
- A. Coppola, J. Stanley, S.J.E. Wilton,
"Interface scheme for connecting a fixed circuitry block to a
programmable logic core", U.S. Patent 6,646,466, Issued Nov
11, 2003.
- C.J. Jones, S.J.E. Wilton,
"Content-addressable Memory with Cascaded Match, Read and Write Logic
in a Programmable Logic Device", U.S. Patent 6,622,204. Issued
Sept. 16, 2003
- C.W. Jones, S.J.E. Wilton, ÒCascadable bus based crossbar
switch in a programmable logic deviceÓ, U.S. Patent 6,590,417, Issued July 8, 2003.