Things you can download:

• The original Poon power model. The power model is best described by this paper.
• An update of the power model for VPR5.0, written by Peter Jamieson. You can read about the power model here
• The enhanced activity estimator for use with the Poon power model.
• Power Aware CAD Tools. This CAD suite contains the EMAP Technology mapper, the P-T-VPACK clusterer, and Place and Route software.
• Benchmark circuits with activities. These are circuits often used in our architectural experiments. Activities are also included.
• Reduced Routing Resource Graph VPR. This is a version of VPR that has a much smaller memory footprint. This is described in this paper.
• Clock-Aware Placement Algorithm for VPR. This version of the VPR placer allows you to specify a wide range of clock networks, and the placment algorithm takes the constraints imposed by these networks into account.
• Analytical Model that describes technology mapping and clustering: This C-implementation of our model is best described by a paper at FPL 2008.
• Interactive CACTI: The Original Cache access and cycle time model