Importing Verilog Into Cadence

Last Updated: Sept. 24, 1997

To import a your HDL design from synopsys to Cadence design frame work II (dfII) follow these instructions (bicmos design kit is used as an example):

• In Synopsys design_analyzer save your HDL design (VHDL, etc.) as Verilog
• Start Cadence by the following command: cds -t bicmos
• When the CIW window appeared, select File->Import->Verilog
• In the Verilog-In form:
1. type in the name of your target library: (it is better to create it first)
2. type in the name of the reference libraries (basic, bicmos, kcells, etc.)
3. type in the name of your verilog file
4. -f : is for verilog options file (don't wory if you don't know what it is)
5. -y: is for -y options (directory paths to be included for Verilog-In)
   Paths must be separated by space.
6. Click ok on VerilogIn form.

This form also allows to load pre-stored information. An example could be find at: /CMC/tools/cadence/local/training/samples/VerilogIn.form
To use a pre-setup form, click Load at the top of the VerilogIn form and when the "Load from" form came up, enter the path to the setup file.

Note: The above sample is for bicmos design kit and for a specific example. You need to modify it for your specific design.