Layout of a CMOS Inverter

This tutorial will guide you through various steps of LAYING out a CMOS inverter.

Introduction

This document contains design guidelines for NT CMOS4S, a 1.2- micron, double polysilicon, double metal N-Well process.

Various Layers in the CMOS Transistors

CMOS transistors are made up of several layers. A brief summary of the MASKS used to generate these layers is given below. The reader can find an extended summary of these masks in the Layout Manual for CMOS4S, provided by CMC.

• N-Well
• Device Well
• P-Guard Exclusion
• Polysilicon
• Capacitor Polysilicon
• N+Doping(Exclusion)
• P+ Doping (Inclusion)
• Contact Windows
• Metal 1
• Metal 2
• Via 1
• Passivation Windows

Various Steps For Laying out an Inverter

A CMOS inverter consists of both P-type and N-type MOS devices on the same common substrate. In the case of CMOS4s, we shall be dealing with an N-Well process. This implies that the substrate is of P-type and an N-Well must be etched into the P Substrate. When you open a window in df II, the plane of the screen represents the P-Substrate. The following steps show you how to layout both PMOS and NMOS on the P type substrate.

LAYOUT OF A CMOS INVERTER

• Place the device wells in the area which shall be active.


• Draw a rectangle on the screen of the N-Well as shown below.



• Surround the N-WEll with the P-Guard.



• Place the polysilicon gates.



• Place the Ndope and Pdope masks, overlapping each other.



• Add Metal1, Contacts, and Split Contacts.



• Connect Input pin to the polysilicon gate.
• Connect the Output pin to the metal 1 wire connecting the drains of the two transistors.
• Connect the Metal 1 to Metal 2 using a "Via". Metal 2 is used for I/O connection purposes only.



• Your CMOS inverter is ready for test and simulation.