• Extension of Verilog which is familiar with Verilog engineer
• Popular in Industry
• Many hardware based libraries
• Synopsys mainly support [5, 6]
• (More Perfectly) Synthesizable
• Learning effort: Middle (for New)

• Not good for hardware modeling as much as VHDL
• Not good for modeling and designing huge size system
    (Complexity of design is higher than SystemC)
• PLI model has not been popular (Failed as a verification methodology !!!)
  

# SystemC [3]

• (C++) + Hardware modeling (Concurrency, timing, signal, port, etc)
• Popular in Research Areass (Many models are written in SystemC) (like VHDL)
• Most Benchmark models are also written in C
• Good for modeling and designing of huge and complex digital system
• Good features of higher language like Polymorphism, Overriding and Instantiation benefit for the complex system
• Co-working with other software engineers is easier
• Cadence mainly support [5, 6]
  
• Need some work to modify for synthesis (convertor), and simulation (Some modification)
• Good for modeling but not good to see waveform
• Good design environment (like Visual C++ 2005) ?
• Learning effort: Easier (for New)

• More positive trends toward SystemC:
  - OCP [4] and many institution and companies are supposed to use SystemC
  - Some NoC model simulators and languages:

Model	Language
gpNoCsim	JAVA	- Downloadable
Netmaker	SystemVerilog	- Downloadable
MPI style NoC simulator (MSNS)	MPI (Message Passing Interface), SystemC	- Downloadable (Sourceforge)
NOXIM	SystemC	- Downloadable (Sourceforge)
NIRGAM	SystemC	- Downloadable
Nostrum	SystemC
OCCN	SystemC	- Downloadable (Sourceforge) - ST Microelectronics et. al.

# My Decision Criteria (for Verification Language)
(I'm using C, JAVA and MATLAB for modeling, VHDL and Verilog HDL for design.)

• Do the design companies support?
• Good for modeling? (Easy?)
• How to simulate with various benchmark codes? (which is based on C generally !!!)
• Valuable for future? Promising? (Usage in industry and research)
  
  => SystemC has been chosen for my NoC simulation to satisfy above requirements

(But both are important and good to know due to their different features.

"SystemC is not optimal language for HDL, and SystemVerilog is not right language for system-level modeling" [7] )

# Some Labs and Tutorials 

[SystemC Lab] University of California

http://twins.ee.nctu.edu.tw/courses/soc_sys_overview_04fall/lab.html

http://users.ecs.soton.ac.uk/ras06r/notes/elec6016/index.html

http://ece.iisc.ernet.in/~bt/systemc/index.html

http://www.asic-world.com/systemc/

http://electrosofts.com/systemC/

http://www.doulos.com/knowhow/systemc/tutorial/

Object Oriented Programming for Hardware Verification [Youtube, presented by Aldec]

# References

[1] www.systemverilog.org

[2] SYNOPSYS, "Transaction-Level Modeling: SystemC or SystemVerilog?",

Available: http://synopsysoc.org/verification/resources/pdfs/tranlvl_systemC_wp.pdf

[3] www.SystemC.org

[4] SystemC OCP Models

Available: http://www.ocpip.org/socket/systemc/

[5] Michael Santarini, "Cadence and Mentor create free, open-source SystemVerilog methodology", EDN, 8/16/2007

Available: http://www.edn.com/article/CA6469179.html

[6] Grant Martin (Cadence Berkeley Labs), "SystemC Tool",

Available: http://www-ti.informatik.uni-tuebingen.de/~systemc/Documents/Presentation-6-OSCI4_martin.pdf

[7] Grant Martin (Cadence Berkeley Labs), "SystemC and the Future of Design Languages: Opportunities for Users and Research" Symposium on Integrated Circuits and Systems Design (SBCCI¡¯03), 2003