Index of /~edc/7660.jan2017/lectures

	Name	Last modified	Size	Description
	Parent Directory		-
	lec1.pdf	2017-06-14 08:32	117K	1 - Introduction to Digital Design with Verilog HDL
	lec2.pdf	2017-06-14 08:32	117K	2 - RTL Design
	lec3.pdf	2017-06-14 08:32	771K	3 - Verilog Expressions
	lec4.pdf	2017-06-14 08:32	65K	4 - Verilog Statements
	lec5.pdf	2017-06-14 08:32	28K	5 - Common HDL Constructs
	lec6.pdf	2017-06-14 08:32	30K	6 - Common HDL Constructs (Part 2)
	lec7.pdf	2017-06-14 08:32	90K	7 - Verification
	lec8.pdf	2017-06-14 08:32	27K	8 - Timing Basics
	lec9.pdf	2017-06-14 08:32	50K	9 - State Machine Design
	lec10.pdf	2017-06-14 08:32	61K	10 - Specifying Timing Constraints
	lec11.pdf	2017-06-14 08:32	46K	11 - Metastability and Clock Domain Crossing
	lec12.pdf	2017-06-14 08:32	320K	12 - ELEX 7660 Project FAQ - Part 1
	lec13.pdf	2017-06-14 08:32	45K	13 - Timing Analysis
	lec14.pdf	2017-06-14 08:32	128K	14 - Programmable Logic Applications and Architectures