Using Synopsys VSS

VHDL designs can be tested by simulation. The tool we will use is Synopsys' VHDL System Simulator (VSS). You must first "analyze" (compile) the test-bench descriptions and your VHDL code into the WORK library using the vhdlan program and then use the vhdlsim program to run the test bench.

Preliminary Steps

  1. Make sure you have added the appropriate lines to the .cshrc.local file in your home directory and have created a vhdl code directory with a WORK sub-directory as described in the instructions on using the Synopsys synthesis software.
  2. Create a file called .synopsys_vss.setup in the vhdl code directory containing the line: 
    DEFAULT : ./WORK
    which will cause compiled files to be placed in the WORK subdirectory. You can either cut and paste the line above or make a copy using the command 
    	cp ~elec464/.synopsys_vss.setup .

Analyze your Code

Analyze the your code using the command (if asg2.vhd is the name of your VHDL file): 
	vhdlan asg2
If your design has syntax errors, edit the source file to correct the errors and run this vhdlan command again.

Analyze the Test Bench

Analyze the test bench code using the command: 
	vhdlan ~elec464/asg2tb
where the file name will depend on the assignment and question. This command compiles the test bench code and saves the result, an entity called "test", in the WORK subdirectory. You must do this once for each new test bench since they will all have the name "test".

Run the Test Bench

To run the test bench and check that your code generates the results that the test bench is expecting, run the command: 
	vhdlsim test
The simulator will then prompt you with the # character. Type run to run the test bench. You can get help on other simulator commands by using the command "help". If there are errors then the behaviour of your code does not agree with what the test bench was expecting. You must figure out why, edit your code, analyze it and run the simulator again (the test bench need not be analyzed again). Use the command "quit" to exit the simulator.

Once you are sure that your design works properly you will need to run vhdlsim again and produce a log file that can be be handed in. Use the command: 

        vhdlsim -s log test
to run vhdlsim and produce a log file ("log") of the results.

Delete Work Files

If you are running short on disk space you can remove all the files in the WORK subdirectory when you are done.
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