Answers to Exercises on Mid-Term Review Lecture
Question 1
truth table:
input output
abc y
000 0
001 0
010 0
011 1
100 0
101 0
110 1
111 0
Sum of Products:
y = ( a* . b . c ) + ( a . b . c* )
where '*' denotes complement, '.' is AND, '+' is OR
VHDL:
entity q1 is
port ( a, b, c : in bit ;
y : out bit ) ;
end q1 ;
architecture rtl of q1 is
begin
process(a,b,c)
begin
y <= ( not a and b and c ) or
( a and b and not c ) ;
end process ;
end rtl ;
OR
architecture rtl of q1 is
begin
process(a,b,c)
begin
if a = '0' and b = '1' and c = '1' then
y <= '1' ;
elsif a = '1' and b = '1' and c = '0' then
y <= '1' ;
else
y <= '0' ;
end if ;
end process ;
end rtl ;
OR any other readily *synthesizable* architecture
Question 2
In this solution the outputs are also used as the state variables
(this is an example of one-hot encoding):
current state input next state next output
T1:4 ALE T1:4' T1:4'
1000 0 0100 0100
0100 0 0010 0010
0010 0 0001 0001
0001 0 0001 0001
XXXX 1 1000 1000
entity q2 is
port ( ale, clk : in bit ;
tout : out bit_vector (1 to 4) ) ;
end q2 ;
architecture rtl of q2 is
signal t, nextt : bit_vector (1 to 4) ;
begin
process(clk,nextt)
begin
if clk = '1' and clk'event then
t <= nextt ;
end if ;
end process ;
process(ale,t)
begin
if ale = '1' then
nextt <= "1000" ;
else
case t is
when "1000" => nextt <= "0100" ;
when "0100" => nextt <= "0010" ;
when "0010" => nextt <= "0001" ;
when "0001" => nextt <= "0001" ;
when others => nextt <= "1000" ; -- can't happen
end case ;
end if ;
end process ;
process(t)
begin
tout <= t ;
end process ;
end rtl ;
Question 3
First exercise:
mov ax,2000H
mov ds,ax
; input byte from i/o address 3fH
in al,3fH
; add byte at 20100H
add al,ds:[100H]
; if sum is zero store 0 else store 1 at 20300H
jz sumzero
mov al,01H
jmp store
sumzero:
mov al,00H
store:
mov ds:[300H],al
The INT 05H instruction loads the vector at 4*5=14H. The LS word
(16 bits) is the IP, the next word is the CS. In both cases the
values are in little-endian order. For example, if the table
had:
address (hex) byte values (hex)
0010 00 10 02 03 40 33 27 34 22 ....
The next instruction executed is the first instruction of the INT
5 ISR at CS=3427 and IP=3340. The physical address is:
34270
+ 3340
-----
= 375B0
The values written to memory by the INT 05H instruction are the
values pushed on the stack. The starting address of the stack
pointer is 10200H. The stack grows downwards and is decremented
before a value is stored so the current PSW will be stored at
101FE, the current CS at 101FC and the current IP at 101FA. The
current IP is the address of the next instruction (the address of
the INT instruction plus 2).
The questions doesn't state either the value of the PSW or the
CS:IP values before the INT instruction is executed (Hopefully I
would remember to give you these in the mid-term). Let's assume
PSW=1234 (may not be a valid PSW value) and CS=1000 and IP=2034
before the INT instruction was executed. The values stored would
be:
phys. byte
address value register
101FF 12 PSW hi
101FE 34 PSW low
101FD 10 CS hi
101FC 00 CS low
101FB 20 IP hi
101FA 36 IP low (address of instruction *following* the INT)
Question 4
The timing diagram for the 8088 during a read cycle (bottom of
page 2-78 in the photocopy of the data sheet) shows the following
happening on the data bus at the falling edge of the clock:
- in T1 the data bus is indeterminate since the address may not
have settled (T_CLAV is positive).
- in T2 the data bus contains the LS 8 bits of the address, in
this case 00H (T_CLAZ is positive).
- in T3 the CPU is doing a read (T_CLAZ is a maximum of 80ns) and
the data bus will either be floating or being driven by the the
memory (the actual value will depend on the timing of the memory
device).
- in T4 the data bus contains the data from the memory device, in
this case 88H.
Question 5
Each 64 kB RAM requires 16 bits of address (A[15:0]). The other
4 address signals are decoded by the address decoder. A PAL
would be sufficient to generate 2 outputs from 4 inputs. It
would probably also have sufficiently low propagation delay and
would be the lowest-cost solution.
[previous (and wrong) answer: ``A 20-bit address value could
probably not be fed to a PAL (which typically have a maximum of
24 pins) so a CPLD would be required.'']
RAM is not OTP. The design of a PAL requires programming a fuse
map with logic equations, not place-and-route. The synthesizer
we've used (Design Compiler) can generate a netlist. In fact,
this was the way we designed FPGAs (the .sxnf file is a netlist).
Question 6
[no specific exercise given]
Question 7
You will need 4 RAM chips in total (64 kB/16 kB). In this case
Ncpu is 32 and the address space for the RAMs is 64kB (16 bits)
thus 16 bits (A31 to A16) need to be decoded for full decoding.
If each RAM is 8 bits wide and the data bus is 32 bits wide then
the 4 RAM chips must be connected in parallel. Only a single
common chip select is needed. The address/data bus connections
are as follows:
CPU A[31:16] address decoder
CPU A[15: 2] each RAM's A[13:0]
CPU D[ 7: 0] RAM0 D[7:0]
CPU D[15: 8] RAM1 D[7:0]
CPU D[23:16] RAM2 D[7:0]
CPU D[31:24] RAM3 D[7:0]
Question 8
After the ISR the value of the IF will be 1 (interrupts will be
re-enabled because the old PSW is popped from the stack).
The timer ISR, at priority level 0, will continue to be executed
because only interrupts of level 1 and lower will be disabled
when the PIC responds to the keyboard interrupt.
The user will not be able to use the keyboard because the PIC
will "think" the keyboard ISR is still in progress and will block
further interrupts at this level.