Answers to Exercises on Final Review Lecture

      Solutions for Exercises on Final Exam Review Lecture

1) DMA

Cycle stealing means that the DMA controller releases the bus
after each byte is transferred.  Transferring 512 bytes would
therefore require that the DMA controller request the CPU bus (by
asserting HRQ) 512 times.  Each byte transferred causes DREQn* to
be asserted so DREQn* will also be asserted 512 times.  Since
data is being transferred from the peripheral to memory, IOR*
will be asserted.

2) Dynamic RAM

DRAM would probably not be a good choice for a small memory for a
portable device because it would require refresh circuitry and
have higher current consumption than SRAM when not being accessed.

If CAS* is asserted before RAS* then a CAS-before-RAS refresh
cycle is being performed.  If during each (burst) refresh 1024
rows are refreshed, then there are 1024 rows.  If the memory
array is square there are also 1024 columns and thus the chip
contains 1 Mbits.

3) Parallel I/O Ports

The CPU data bus (DB[0:7]) can be connected directly to the
peripheral's data inputs (D[0:7]).

The peripheral's DONE output can be connected to bit 7 of the
CPU's data bus (D7) using a tri-state buffer whose output enable
is controlled by AND'ing the peripheral chip select (CS) and the
CPU's R/W* signal.

(see diagram)

4) SCSI Interface

SEL*	BSY*	data*	C*/D	I*/O

Bus Free

F	F	X	X	X

Selection

T	X	20	X	X
X	T	X	X	X

Command Phase
F	T	08	T	F
F	T	00	T	F
F	T	00	T	F
F	T	00	T	F
F	T	01	T	F
F	T	00	T	F

Data Phase

F	T	34	F	T
F	T	78	F	T
F	T	55	F	T
F	T	12	F	T

Status Phase

F	T	00	T	T

Bus Free

F	F	X	X	X


All of the above signals are active-low and "T" refers to the
following:

SEL* = low = select
BSY* = low = busy
Control*/Data = low = control
Input*/Output = low = input (initiator inputs from target)

and "X" is "don't care"