ELEC 464 Course Outline

ELEC 464 : Microcomputer System Design

Instructor

Ed Casas. I am normally on campus only during lectures, tutorials and office hours. The best way to contact me at other times is by e-mail: edc@ece.ubc.ca.

Lectures

Tuesdays and Thursdays, 10:30 -- 11:30 am. MCLD 202. Lectures start September 5 and end November 30.

Office Hours

Tuesdays and Thursdays, 12:30 -- 1:30 in MCLD 155. The times may vary depending on demand.

Tutorials

Fridays 3:30 -- 4:30 pm. MCLD 202. The tutorials will be used to review particularly difficult lecture material and to solve problems from the assignments.

Teaching Assistants

Atousa Soroushi atousas@ece.ubc.ca and Dejan Kusalovic dejank@ece.ubc.ca will mark the assignments and possibly run some tutorials.

The newsgroup ee.elec464 will be used to post announcements about the course. This newsgroup is currently available only on the EE news server. Students are also encouraged to post questions or comments relating to the course.

Prerequisites

Student should have experience in the design of simple digital circuits and have done some machine language programming using the Motorola 68000 or a similar microprocessor.

Objectives

By the end of the course the student should have sufficient background to design a microprocessor-based system using standard commercial ICs. In particular, the student should be able to:

analyze the operation of 68000 processor bus signals and cycles including the timing of read and write cycles
design combinational and sequential interface circuits such as address decoders and wait state generators
describe and simulate those circuits using a simple hardware description language (CUPL)
describe the characteristics of common IC memories (SRAM, DRAM, EPROM) devices including their timing requirements
describe in detail the response of a 68000 processor to the most important exceptions (interrupt, trap, bus error, etc.)
select an appropriate i/o strategy (polled, interrupt, or DMA) for a given application
describe the characteristics of common peripheral buses
write device driver software to support typical I/O devices using different I/O strategies and verify it using a 68000 emulator

Text

Alan Clements: Microcomputer System Design: 68000 Hardware, Software and Interfacing . Second Edition. PWS-Kent, 1992. This text was used for this course last year.

Another Useful Reference

The Art of Electronics, second edition, by Paul Horowitz and Winfield Hill, Cambridge University Press, 1989, is a good practical reference book on most aspects of electronics. Available in the UBC library as well as the bookstore.

Assignments

An assignment will be given out each week. Solutions will be given out for all questions but not all questions will be marked.

Evaluation

There will be one mid-term examination (1 hour) in late October (date TBD). The final mark will be calculated as follows:

	final exam 	60%
	midterm exam	30%
	assignments	10%

Course Outline

course outline, introduction (Ch 1)
review of Motorola 68000 CPU architecture and instruction set (Ch 2, 3)
review of combinational and sequential logic, programmable logic devices, PAL design examples
68000 address, data and control bus, bus cycles (Ch 4)
memory technology, timing considerations, wait state generation, DRAM interfacing and refresh (Ch 4, 5, 7.2)
interrupt and exception handling (Ch 6)
DMA (Ch 8.2)
cache and virtual memory systems (Ch 7.4, 7.5)
peripheral buses: parallel and serial interfaces (Ch 9)
the IBM PC and VME buses (Ch 10)
overview of the Intel 8088 architecture, instruction set and processor interface

The Motorola 68000

Although the Motorola 68000 microprocessor is obsolete we will use it as an example throughout this course. The 68000 has many of the features present in more modern CPUs and most students have used the 68000 in previous courses. The 68000 architecture lives on as the CPU core in the Motorola 68300 series of 16-bit microcontrollers.

Ed Casas / edc@ece.ubc.ca