Question 1

There should be an input to your circuit from the peripheral
requesting the interrupt.  This input is not mentioned in the
question.  You can label it whatever you want.

It might help to draw a truth table before drawing the schematic.

			   Question 2

Your circuit need not handle the cache update function.

Your circuit should not extend the read cycles longer than
required by the memory devices.

RD* is not directly controlled by WAIT*.  You can assume that a
read cycle will last for one clock cycle even if WAIT* is not
asserted. Thus the CPU will hold RD* low for about one clock
cycle regardless of the value of WAIT*.  If WAIT* has been
asserted at the end of the first cycle then RD* will remain low
until WAIT* is de-asserted.

A practical circuit would have to assert the MAIN* and CACHE*
enables for at several tens of ns (in practical terms, at least
one clock cycle) before the end of the read cycle.  It would be
nice if your circuit did this.

You don't have to worry about interaction between adjacent
read/write cycles. [If you want to worry about it you can change
the specification from ``RD* remains asserted until WAIT* is
de-asserted'' to ``a read cycle is extended by another clock
cycle when WAIT* is true at the end of a clock cycle.''  Please
indicate on your answer if you make this assumption.]