Marking of Assignment 3

Question 1 was marked in two parts and counts as two assignments. Each part was marked out of 10. Marks were assigned as follows:

Part 1

• 1 for package defining two 8-bit types
• 1 for ROM VHDL code
• 2 for ROM simulation showing contents of all 10 addresses
• 1 for comments in RAM VHDL
• 2 for RAM simulation showing correct operation of the 3 write and the 3 read cycles
• 1 for PC VHDL code
• 2 for PC simulation results showing correct results for the 3 possible commands (hold, increment,jump)

Part 2

• 1 for ALU VHDL code
• 2 for ALU simulation showing correct execution of the 6 ALU operations
• 1 for instruction decoder VHDL code
• 2 for decoder simulation results for each instruction, including jump/no jump results for each conditional jump (total of 10 tests)
• 1 for top-level VHDL code
• 3 for final simulation results showing correct CPU execution including conditional and infinite loops