Hints for Lab 4
Lab 4 is time-consuming and requires
attention to detail. You will not finish it if you don't come
fully prepared or make too many mistakes. Here are some common
errors:
- Preparation:
- coming to the lab late
- coming to the lab without working and tested VHDL
- not having an ACF file prepared
- VHDL errors:
- wrong polarity for the data, start or stop bits
- not resetting the clock divider when load is asserted
- not changing the clock divider ratio from 2 back to 2622
- Wiring:
- connecting serial interface or logic analyzer
grounds to the wrong wiring strip
- connecting the serial output on FPGA pin 109
to PC-104 bus signal IRQ 7
- Max+Plus II Configuration:
- not assigning one or more signals to pins or to the wrong pins
- using SYSCLK instead of the internal clock
- configuring the data bus signals as Input instead of Bidirectional
- Software:
- reversed logic in the assembly program for testing the "done" signal
Your setup will almost certainly not work the first time and you
will have to debug it. Hook up the logic analyzer to the address
bus, data bus, IOR*, IOW* and the serial output. Check to see if
your program reads the correct value (01H) from 221H. Check to
see if it writes the correct value (the ASCII value of the first
letter of your name) to 220H. If port reads and writes are
working properly you will probably see something on the Hyperterm
window monitoring COM2. If the string is incorrect, set the
sampling rate to 100 kHz and check the serial output.
The output of the serial output mux may have glitches. Although
the serial port will work properly, glitches in an output are
undesirable. To get rid of the glitches you can register the
output by connecting a flip-flop (in VHDL, of course) between the
mux output and the serial output. Clock this FF with the 25 MHz
clock.
You will probably find it easier to fix errors in the VHDL code
if your design is contained in just one or two files.
ELEC 379 Home Page