Name | Last modified | Size | Description | |
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Parent Directory | - | |||
exam.pdf | 2000-04-14 16:12 | 133K | Final Exam | |
lec1.pdf | 2000-01-04 20:29 | 62K | Introduction to Logic Design with VHDL | |
lec2.pdf | 2000-01-14 09:36 | 66K | 386SX Processor Bus/Instruction Set | |
lec3.pdf | 2000-01-26 02:11 | 211K | RTL Design with VHDL | |
lec4.pdf | 2000-02-28 08:18 | 44K | Interrupts | |
lec5.pdf | 2000-03-10 00:40 | 213K | Memory, Timing Analysis | |
lec6.pdf | 2000-03-28 21:11 | 93K | DMA, Buses | |
midsol.pdf | 2000-02-28 18:37 | 10K | Mid-Term Exam Solutions | |
midterm.pdf | 2000-02-27 23:50 | 11K | Mid-Term Exam | |
review.pdf | 2000-02-23 08:10 | 8.4K | Mid-Term Review | |