library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;

package cputypes is
  subtype dword is unsigned (7 downto 0) ;
  subtype iword is std_logic_vector (7 downto 0) ;
end cputypes;

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.cputypes.all ;

entity ram is 
	port (
	din : in dword ;
	a : in std_logic_vector (4 downto 0) ;
	write, clk : in std_logic ;
	dout : out dword
	) ;
end ram ;

architecture rtl of ram is
	type dataarray is array (31 downto 0) of dword ;
	signal ramarray : dataarray ;
	signal d, nextd : dword ;
begin

	d <= ramarray (conv_integer(unsigned(a))) ;
 
	nextd <= din when write = '1' else d ;

	process(clk)
	begin
		if clk'event and clk = '1' then
			ramarray(conv_integer(unsigned(a))) <= nextd ;
		end if ;
	end process ;

	dout <= d ;

end rtl ;