The numbers in parentheses indicate the number of marked items (1
mark each).

			      Labs

Lab 1 Pre-Lab (3)

- identification information
- VHDL source (reasonably complete)
- correct answer for second question (the selected value for both
  buttons pushed: when select value = 00)

Lab 1 Report (3)

- VHDL code (with "11" selecting the first two digits of your ID)
- flow summary capture
- RTL netlist showing multiplexers only

Lab 2 Pre-Lab (4)

- a labelled state transition diagram
- reasonably complete VHDL code
- answer to question 1 (when release Key(0) because it is
  active-low)
- answer to question 2 (press key(1) when release key(0) because
  it's a synchronous reset)

Lab 2 Report (3)

- VHDL
- Flow summary
- block diagram

Lab 3 Pre-Lab (2)

- state transition diagram
- VHDL code

Lab 3 Report (2)

- VHDL code
- screen capture and netlist

Lab 4 Pre-Lab (3)

- table showing enough states and outputs
- state transition diagram with transition conditions
- reasonable approximation to working VHDL code

Lab 4 Report (2)

- VHDL code
- screen capture and netlist

Lab 5 Pre-Lab (1)

- a reasonable approximation to a correct solution: must at least
  have the correct I/O declarations and a state machine for
  scanning rows

Lab 5 Report (1)

- (working) VHDL code

Lab 6 Pre-Lab (2)

- correct sequence of values
- VHDL code

Lab 6 Report (3)

- VHDL code
- compilation report
- RTL block diagram


			   Assignments

Assignment 1 (11)

Q1(a): 
- an entity with correct i/o modes and names
- an architecture with 1+ concurrent assignment(s)
- process(es) with 3+ assignments in (two ffs and output)

Q2(a):

- a state transition diagram or table with 4+ states or
  register(s) with 2+ bits

Q2(b):
- an entity with correct i/o modes and names
- an architecture with 1+ concurrent assignment(s)
- process(es) with 1+ assignments


Q3(a):
- state transition diagram with 6+ states
Q3(b):
- an architecture with 2+ concurrent assignment(s)
- process(es) with 2+ assignments in (for state, pout)
- a schematic where number/size of registers/ffs matches the VHDL


Assignment 2 (8)

Q1

- includes a schematic with three 2-input muxes in right order
  (first stage selecting 1 or 255) feeding...
- an 8-bit register

Q2
- includes a 4-way selected assignment with x"F" as the "others"
  result

Q3
- a 3-clause conditional assignments with the last two results
  being freq*2 and freq+1

Q4
- assignment for next-state tests 'stop' input and selects...
- a state where both outputs are off

Q5
- a conditional/selected assignment based on a count value of 0,
  19 or 20

Q6
- a transition to state A (G=1,Y=0) when en and f are '1'




			  Mid-Term Exam

Question 1 (8)

One mark was assigned for each of the following essential
elements of a correct solution:

- the code includes an entity and an architecture

- the entity includes in/out mode signal declarations


- the architecture includes internal signal declarations

- the architecture includes a conditional or selected assignment


- the selected/conditional assignment includes a condition that
  sets the count to zero

- the selected/conditional assignment includes an expression that
  decrements a signal


- the architecture includes a process statement

- this process statement includes a correct sensitivity list, if
  statement and a *simple* assignment

Question 2 (4)

One mark was assigned for each of the following requirements:

- uses 2 or more multiplexers

- input and output signal and control names are correct

- correct mux order (the first tested condition is nearest
  output)

- an xor gate or mux controlling the correct mux


			   Final Exam

Question 1 (10)

- an entity declaration with the correct name (controller)
- port clause with correct names, in/out modes and signal types
- architecture declaration with correct 'of' clause and a
  begin/end
- unsigned register signal declaration with correct number of
  bits (not N, not 2**N)
- register (or output) reset code
- register incremented if not reset
- process statement with correct sensitivity list and if
  statement
- assignment to register value
- conditional assignment for first output
- conditional assignment for second output

Question 2 (8)

- an entity declaration with the correct name (controller)
- port clause with correct names, in/out modes and signal types
- architecture declaration with correct 'of' clause and a
  begin/end
- first clause in conditional assignment is for reset
- second clause in conditional assignment is to
  increment/decrement
- third clause to hold value
- process statement with clk in sensitivity list and if statement
  and correct signal assignment (usually something like x <=
  x_next where x_next is assigned by combinational logic)
- declares and uses a separate signal to avoid reading signal of
  mode out

Question 3 (6)

- includes a mux for the reset function with the correct constant
  reset value
- includes a mux for the increment/decrement function with the
  correct increment/decrement function block
- includes a register with a clock signal
- the reset mux is closest to the register
- the mux and register output widths are correctly labelled
- signal name labels (mux control and register in/out) are
  correct