ELEX 2117 - Digital Techniques 2

• Announcements
• Course Information
• ELEX 2117 Course Information
• marking
• indent
• Software Installation and Use
• Report and Video Guidelines
• Coding Guidelines
• ELEX2117Template.dotx

  Microsoft WordTemplate you can use for lab reports.

• ELEX2117Usage.docx

  Instructions and examples on how to use the report template.

• Cover Page Example for Lab0

  Example Lab 0 report cover page.

• Lectures
• Lecture 1 - Introduction to Digital Design with Verilog HDL
• Lecture 2- Flip‑Flops and Registers
• Lecture 3 - State Machines

  Revision 3.

• Lecture 4 - More Verilog
• Lecture 5 - Interfaces
• Lecture 6 - Timing Analysis

  Revised March 11.

• Lecture 7 - Memory System Design
• Lecture 8 - Verification
• Lecture 9 - Implementation of Digital Logic Circuits
• Lecture 10 - Programmable Logic Applications and Architectures
• Summary of Learning Objectives
• Labs
• X2117_LabRules_Approved
• Lab 0
• Lab 0 - Practice Lab
• lab0demo.mp4
• lab0.pof

  Program this file to test your hardware.

• Lab 1
• Lab 1 - Combinational Logic Design with Verilog
• lab1demo.mp4
• lab1.pof

  Program this file to test your hardware.

• Lab 2
• Lab 2 - Sequential Logic Design with Verilog
• clkdiv.sv

  You'll need to add this file to your project to generate a 200 Hz clock.

• lab2demo.mp4

  Demonstration video for Lab 2.

• lab2.pof

  Program this file to test your hardware.

• Lab 3
• Lab 3 - Matrix Keypad Decoder
• lab3demo
• lab3.pof
• Lab 4
• Lab 4 - Timers and Clock Dividers
• lab4demo.mp4
• lab4.qsf
• lab4.pof
• Lab 5
• Lab 5 - Hierarchical Design
• lab5modules.sv
• lab5demo.mp4
• lab5.pof
• lab5.qsf
• Lab 6
• Lab 6 - Asynchronous Serial Interface
• lab6a.qar - Lab 6b Quartus archive
• lab6.pof
• Lab 6b
• Lab 6 (b) - Asynchronous Serial Interface Receiver
• lab6b.mp4- Sample Demo Video
• lab6b.qar - Lab 6b Quartus archive
• lab6.pof - to test your hardware
• Lab 7
• Lab 7 - Digital Waveform Measurement
• Lab 8
• Lab 8 - Logic Level Conversion
• Lab 9
• Lab 9 - Simulation
• lab9.sv
• lab9_tb.sv
• lab9testdata.zip
• Videos
• Installing Quartus

  Note: download and install MAX II instead of Cyclone IV device support files.

• Using Quartus for Logic Synthesis

  Note: select the EPM240T100C5 device (you can filter on the MAX II device family, TFQP package, 100 pin and speed grade 5).

• Simulation with Modelsim
• Exercise Answers
• lec1-exercises
• lec2-exercises
• lec3-exercises
• lec4-exercises
• lec5-exercises-completed
• lec6-exercises-completed
• lec7-exercises-completed
• lec8-exercises-completed
• lec9-exercises-completed
• lec10-exercises-complete
• Quizzes and Exams
• Quiz 1
• Solutions to Quiz 1
• Midterm Exam 1
• Solutions to Midterm Exam 1
• Quiz 2
• Solutions to Quiz 2
• Midterm Exam 2
• Solutions to Midterm Exam 2
• Solutions to Quiz 3

  The answer to Question 4 part b was corrected on April 13 (the number of banks is 2).

• Final Exam
• Solutions to Final Exam
• Datasheets

  These may or may not be the datasheets for the components we will be using.

• FJ-5463 4-digit 7-segment LED Display
• "USB-Blaster" Schematic (STM32 version)
• Resources
• Verilog
• Verilog Papers

  Links to some additional [System] Verilog resources.

• Other
• Parts Kits Contents
• Student Evaluations