"Open Lab" Demonstrations

The purpose of an "open" lab at the end of the course is to allow students to make up a lab that they were unable to complete during the course. Students may submit documentation to show they completed one additional lab on their own.

The restriction to one lab is to keep to the original intent of the open labs and to limit the workload for the faculty.

The purpose of the pre-lab assignments was to prepare for the lab. Thus marks will not be awarded for the pre-lab part of each lab's mark. However, as a special case, if you did not complete the pre-lab for Lab 5 you may submit it as well.

You should submit the following files to the "Open Lab" assignments folder if you wish to "demonstrate" one of the following incomplete labs.

Please keep the sizes of the videos reasonable (please use the minimum resolution your camera supports).

Since the "open lab" was scheduled for April 8, the deadline for submitting these files is 5:30 PM on April 8.

Lab 1

Lab 2 Demonstration

No preparation mark will be awarded for this lab if submitted for the "open" lab.

To get a mark for demonstrating Lab 2, upload your VHDL code and two videos:

1. one showing the operation according to the sequence corresponding to the last digit of your student number as given in the entry in the table on page 2. Your video should show the pushbutton and the LED array (or individual LEDs).
2. one showing the operation according to the next entry in the table on page 2 (and if you did a modulo-3 down-counter also show a binary up-counter in your second video).

Lab 3 Demonstration

To get a mark for demonstrating Lab 3, upload your VHDL code and two videos showing:

1. • the display cycling through all of the digits of your student number as you press the clock button.
   • the display being reset to the first digit (from some other value) when holding the reset button and pressing the clock button.
2. as above but showing the digits of your student number in reverse order.

Lab 4 Demonstration

To get a mark for demonstrating Lab 4 upload your VHDL code and two videos showing the following:

1. that the circuit displays the correct value and does not start counting down when reset (when reset held and clock pushed), counts down when run_stop is pushed, stops when pushed again, restarts when pushed a third time, resets the time remaining and stops when reset_n is pushed, turns on the alarm led when the count reaches zero, and the alarm turns off when run_stop is pushed.
2. if the last digit of your student ID is even, your circuit showing a different initial timer value, if the last digit of your student ID is odd, your circuit running half as fast (changes value once every two seconds)

Lab 5 Pre-Lab

1. Block diagrams of the CPLD functional blocks (see lab notes).
2. A schematic, including pin numbers, showing the CPLD connections to the pushbutton switches and to the 7-segment LED display.
3. The VHDL code for your design, commented as described in the previous lab.

Lab 5 Demonstration

1. • pressing and releasing only the left button causes the time to increase by 1
   • the value does not increase past 15 (F)
   • pressing and releasing only the right button causes the time to decrease by 1
   • the value does not decrease past 0
   • pressing both buttons and releasing them makes the timer start
   • pressing both buttons and releasing them makes the timer stop
   • pressing both buttons and releasing them makes the timer start
   • when the count reaches zero it stops and the alarm goes on
   • pressing both buttons turns off the alarm
2. a modified version showing that the counter value cannot be increased to a value larger than the largest digit in your student ID (e.g. if your ID is A00123456 then the largest time value should be 6)

Labs 6, 7

See lab instructions for what you need to submit if you decide to submit one of these labs as your open lab.