The numbers in parentheses indicate the number of marked items (1
mark each).

                               Quizzes

                          Quiz 1 (out of 37)

Q1 (13):

- per correct value at each of 5 transitions: 5
- per correct entry in truth table: 8

Q2 (14):

- per correct specification name: 7
- per correct variable name *or* R/G: 7

Q3 (2):

- correct expression: 1
- correct value: 1

Q4 (8):

- per correct value at t2: 4
- per correct value at t4: 4

                          Quiz 2 (out of 19)

Q1 (10):

(a) 1 for logic
(b) 1 for mux and inputs, 1 for control logic
(c) 1 for FF, 1 for inputs/outputs
(d) 1 for each mux (2), 1 for FF, 1 for each logic controllng the muxes (2)

Q2 (9):

(a) 1 for expression
(b) 1 for when, 1 for else
(c) 1 for y_next expression, 1 for FF
(d) 1 for FF
(e) 1 for each clause (3)


                          Quiz 3 (out of 14)

(a) 1 mark per state (4)
(b) 1 mark per transition condition (6), 1 mark for a diagram
(c) 1 mark per output equation (3)


                              Quiz 4 ()

(a) states (either named or included in state transition diagram):
    1 for 1 or more
    2 for 2 or more
    3 for 4 or more (required for correct operation)

(b) state transitions
    1 mark if have button in one state transition
    1 mark if have t5s in one transition
    1 mark if have t15s in one transition
    1 mark if have 3 or more state transitions
    1 mark if have 4 or more state transitions

(c) 1 mark for each output expressions that is only a function of the
    state and the inputs


                          Quiz 5 (out of 12)

- one mark per question (submitted and marked on-line)


			      Labs

Lab 1 - Week of Jan 13 (4)

- one mark for each correct measurement (4 total)

Lab 2 - Week of Jan 20 (2)

- Pre-Lab
- Demo

Lab 3 - Week of Jan 20 (3)

- Pre-Lab
- Demo 1
- Demo 2 (there should be one check mark for each demo)

Lab 4 - Weeks of Feb 3 and 10 (3)

- Pre-Lab
- Demo 1
- Demo 2 (there should be one check mark for each demo)

Lab 5 - Weeks of Feb 17 and 24 (2)

- Pre-Lab
- Demo

Lab 6 (2)

- one mark for submitting reasonable VHDL code 
- one mark for the video demo

Lab 7 (4)

- screen capture of waveform shows the required initial input (x)
  sequence at the start (x=0, 7, 8, 9)

- screen capture of waveform shows the required ending input (x)
  sequence (x=the digits of your student number)

- screen capture of transcript (-0.25 per "line ... expected ..."
  warning message)

- VHDL file conforming to course coding guidelines, including comments
  at beginning
  
 Lab 8 (5)

- a block diagram with three registers (one for the state, one for the
  bits and one for ss_n)

- a VHDL file with comments at the beginning and no serious deviations
  from the course coding guidelines

- a screen capture showing the simulation waveforms (the values are
  not checked -- the validity of the output waveforms is checked by
  the testbench)

- a transcript showing that the values transmitted over the serial
  interface correspond to the last three digits of the student’s BCIT
  ID (2 marks if the received digits match and there are no “serial
  receive aborted” warnings, 1 if digits match and there are
  warning(s), 0 if the digits don’t match)



                               Lab Exam

The lab exam was marked as follows:

- a working circuit (marked out of 5, worth 50%):

  - subtracted 1 mark per incorrect output value

  (Almost all students obtained full marks for this part.  A couple of
  students reversed the switches and a couple omitted the register
  from their VHDL)

- block diagram is complete and unambiguous (marked out of 5, worth
  25%):

  - one multiplexer for each state to select next state, with correct
    inputs (2)
  - multiplexer to select next state with labelled inputs
  - state register with clock input
  - multiplexer or ROM to select output for each state

  (Many students lost a mark for not including in their diagrams the
  logic that generates the output as a function of the state -- this
  is asked for in the lab exam instructions.).
  
- VHDL is complete and complies with the course VHDL coding guidelines
  (marked out of 5, worth 25%):

  - synchronous (all condional and selected assignemts have a final
    else or others clause)
  - doesn't use process statements
  - explicit register input signals named _next
  - only 1164 types (std_logic,...)
  - a comment with the student's name at the start of the file

  (Many students lost a mark for not including their name in comments
  at the beginning of the file even though there's a comment asking
  for this there and file-level comments are *required* by the course
  VHDL Coding Guidelines.)


			  Midterm Exam 1

Question 1 (6)

- timing diagram marked out of 5; -1 per incorrect transition

- truth table marked out of 9 (JK) or 11 (T); -1 per incorrect entry

- sum (14 or 16) is scaled to 6 and rounded

Question 2 (6)

- subtract 0.5 marks for each incorrect/missing specification name and
  each incorrect/missing R/G value in the table (the symbol was not
  marked); setup time was marked correct if specified as a propagation
  delay.

Question 3 (2)

- 1 mark for correct calculation method
- 1 mark for the correct result

Question 4 (2)

- 0 marks if work not shown (just a sequence of values), or if the
  answer was ambiguous (multiple sequences given with no box around
  one -- see instructions), or if only the final value gives (the
  question asks for the value_s_(plural)
  
- otherwise 1 mark if values incremented and 1 mark if values do not
  exceed 3 (at correct clock edge)


			  Midterm Exam 2

Question 1 (6)

- adequate number of states (2 marks; no marks if not enough states)

- correct state transitions (2 marks, one for transitions with
  reset=1, one for transitions with fault=1)

- an expression for the output (2 marks, if assigns to warn based on
  state (and optionally, inputs); no marks if don't assign to the
  output (named 'warn') or if assign a state(!) to the output)

Question 2 (6)

- nand (1)
- mux (2)
- 3-way mux (2) (-0.5 if mux inputs not labelled; -1 if order reversed)
- FF (1)

Question 3 (8)

- (a) through (d): 1 mark each (4)
- (e): -1 if conditional test was wrong (inverted sense); 1 per
  other major error (4)

Typical problems on Midterm 2 Question 1 (State Machine Design):

- not answering the question
 - writing out next-state equations
 - drawing block diagrams
 - not giving an expression for the output
- ambiguous answers (not reading the instructions)
- ignoring hints (assuming only as many states as output combinations, i.e. only 2)
- assuming inputs that aren't there (e.g. a count of number of faults)
- assigning states to outputs (*really* don't understand what's going on)
- multiple answers to show how smart you are (even if both are right)

			   Final Exam

- this was a Learning Hub quiz marked out of 35.  The marking is
  available at Activities > Quizzes > (in Final Exam under Evaluation
  Status column) On Attempt > Attempt 1.