ELEX 2117 - Digital Techniques 2

• Announcements
• Course Information
• ELEX 2117 Course Information
• Software Installation and Use
• Report and Video Guidelines

  Version 2: Simplified rules for block diagrams.

• Coding Guidelines
• marking
• indent
• ELEX 2117 Report Template (MS Word)
• ELEX 2117 Report Example (MS Word)
• draw.io diagram editor
• Lectures
• Lecture 1 - Introduction to Digital Design with Verilog HDL
• Lecture 1 - Introduction to Digital Design with Verilog HDL (rev. 2)

  Version 2: Re-ordered and revised sections on Arrays of Arrays and Statements.

• Lecture 2 - State Machines
• Lecture 3 - More Verilog
• Lecture 4 - SImulation
• Lecture 5 - Interfaces

  Revision 2:  Changed SPI example to msb-first; added state to controller timing diagram.

• Lecture 6 - Timing Analysis
• Lecture 7 - Implementation of Digital Logic Circuits
• Lecture 8 - Analog Interfaces
• Lecture 9 - Programmable Logic Applications and Architectures
• Labs
• Lab 0 - Practice Lab
• Lab 1
• Lab 1 - Combinational Logic Design with Verilog
• lab1.pof

  If you used the same pinouts as in the lab notes you can program your CPLD with this file to check that your hardware is working correctly.

• lab1demo.mp4

  Example video.

• Lab 2
• Lab 2 - Sequential Logic Design with Verilog
• clkdiv.sv

  You'll need to add this file to your project to generate a 200 Hz clock.

• lab2.pof

  Program this file to test your hardware.

• lab2demo.mp4

  Demonstration video for Lab 2.

• Lab 3
• Lab 3 - Matrix Keypad Decoder

  Note that this lab is subtly different than last year's Lab 3.

• lab3.pof
• lab3demo.mp4
• Lab 4
• Lab 4 - Timers and Clock Dividers
• lab4demo.mp4
• lab4.pof
• lab4.qsf
• Lab 5
• Lab 5 - Simulation
• lab5tv.xls

  Spreadsheet to generate test vectors.

• Lab 6
• Lab 6 - SPI Interface

  Revision 2: added bypass capacitor, MISO delay to block diagram, simulation example, and use of keypad 2 to reset.

• lab6-incomplete.sv

  Revision 3: Revised November 8 to fix timing of shift control signal relative to state (it was early by one clock period).  Revised again to fix MISO timing offset (not used in this lab) and remove redundant test vector signals.

• lab6.qsf
• lab6tv.csv

  Revision 3 (to match Revision 3 of lab6-incomplete).

• lab6.pof

  Revision 3 (to match Revision 3 of lab6.sv).

• Lab 7
• Lab 7 - Logic Level Conversion and Digital Waveform Measurements

  Version 2: View inverted waveforms on TP1 and TP3 (not TP2).

• Lab 8
• Lab 8 - D/A and A/D Conversion
• lab8-incomplete.sv

  Rename to lab8.sv and add your code to this file.

• lab8.qsf

  You can import pin assignments and other settings from this file.

• lab8demo.mp4
• Videos
• Installing Quartus

  Note: download and install MAX II instead of Cyclone IV device support files.

• Using Quartus for Logic Synthesis

  Note: select the EPM240T100C5 device (you can filter on the MAX II device family, TFQP package, 100 pin and speed grade 5).

• Simulation with Modelsim
• Exercise Answers
• lec1-exercises
• lec1b-exercises

  Revision 2.

• lec1-exercises-filled
• lec2-exercises
• lec2-exercises-filled
• lec3-exercises
• lec3-exercises-filled
• lec4-exercises
• lec4-exercises-filled
• lec5-exercises
• lec5-exercises-filled
• lec6-exercises
• lec6-exercises-filled
• lec7-exercises
• lec7-exercises-filled
• lec8-exercises
• lec8-exercises-filled
• lec9-exercises
• lec9-exercises-filled
• Quizzes and Exams
• Quiz 1
• Solutions to Quiz 1
• Midterm Exam 1
• Solutions to Midterm Exam 1

  Revision 2: Added reset!=0 transition conditions in Question 5.

• Quiz 2
• Solutions to Quiz 2
• Midterm Exam 2
• Solutions to Midterm Exam 2
• Quiz 3
• Solutions to Quiz 3
• Final Exam
• Solutions to Final Exam
• Resources
• Verilog
• Verilog Papers

  Links to some additional [System] Verilog resources.

• Student Evaluations