ELEX 2117 - Digital Techniques 2

• Announcements
• Course Information
• Course Information
• Contact Information
• Marking Scheme
• Verilog Coding Guidelines

  Version 2, in effect starting with Lab 5.

• Checking and Converting Video Files
• Lectures
• Lecture 1 - Introduction to Digital Design with Verilog HDL
• Lecture 2 - Flip-Flops and Registers
• Lecture 3 - HDL Idioms
• Lecture 4 - State Machines
• Lecture 5 - System Verilog
• Lecture 6 - Interfaces
• Lecture 7 - Static Timing Analysis
• Lecture 8 - Memory System Design
• Lecture 9 - Verification
• Lecture 10 - Implementation of Digital Logic Circuits
• Lecture 11 - Programmable Logic Applications and Architectures
• ReviewLecture
• Summary of Learning Objectives
• Exercise Answers
• lec1-exercises
• lec2-exercises
• lec3-exercises
• lec4-exercises
• lec5-exercises
• lec6-exercises
• lec7-exercises
• lec8-exercises
• lec9-exercises
• lec10-exercises
• lec11-exercises
• Labs
• Lab 1 - Combinational Logic Design with Verilog
• lab1demo.mp4

  Sample video submission for Lab 1.   Rest your phone on something (e.g. a mug) to prevent camera shake.  This 6-second MP4 video at 640x480 (about 400 kB) is adequate to demonstrate your lab.  

• Lab 2 - Sequential Logic Design with Verilog
• debounce.sv

  Download this file to your project folder and add it to your project.  This will allow you to instantiate a switch debouncer into your design.

• lab2demo.mp4

  Sample video for Lab 2.

• Lab 3 - Timers and Clock Dividers
• lab3demo.mp4
• Lab 4 - Multiplexed Display

  This is version 3, it includes an optional alternate current-limiting resistor configuration and the correct resistor values (200 ohms).

• Lab 5 - BCD Counters
• lab5.qar

  Download this  archive file and open it with Quartus to create an (incomplete) project for Lab 5.

• lab5demo.mp4

  Sample video submission for Lab 5.

• Lab 6 - Quadrature Encoder Decoding

  Version 2: Added examples of state transition and output tables for the decoder state machine.

• lab6demo.mp4

  Sample video submission for Lab 6.

• Lab 7 - SPI Interface
• lab7.mp4

  Sample video submission for Lab 7.

• lab7.qar

  Download this  archive file and open it with Quartus to create an (incomplete) project for Lab 7.

• lab7.pof

  If you used the pin assignments in the lab instructions then you can program your CPLD with this .pof file to check that your hardware is working correctly.

• Lab 8 - Simulation
• lab7_tb.sv

  The simulation testbench for Lab 8.

• tb_debounce.sv

  Debouncer with zero delay (connects input to output).

• Lab 9 - Digital Signal Measurement
• Exams
• Quiz 1b Answers
• Software
• Intel FPGA Software

  This is a link to the Quartus Prime software to synthesize your designs and program the CPLD.  Modelsim will be used for simulation.   Download and install Quartus Prime, ModelSim-IntelFPGA Edition, and the MAX II device support.   If you've already installed version 13.0sp1 from a previous course it will probably be fine (and be faster as well).  The lab instructions will be written for version 20.1 but the procedures should be very similar for version 13.0sp1.  You can have multiple versions installed at the same time.

• Resources
• Verilog
• Verilog Papers

  Links to some additional [System] Verilog resources.

• Other
• ELEX 1117 Parts
• ELEX 2117 Parts
• Including Code in Reports
• Fixing Display Problems in Quartus
• Using Your Browser as a Calculator
• Troubleshooting USB-Blaster Problems