About Me

I am a Master's student sutdying at the University of British Columbia under Prof. Guy Lemieux. My research interests are in FPGA CAD tools, especially in the area of interconnect variation. I completed my undergraduate degree in computer engineering at UBC in 2006.



D. Chiu, G. Lemieux, Congestion-Driven Re-Clustering CAD Flow for Low-Cost FPGAs

D. Yeager, D. Chiu, G. Lemieux, "Congestion Estimation and Localization in FPGAs: A Visual Tool for Interconnect Prediction", Proceedings of the 2007 international workshop on System level interconnect prediction, p.33-40, March 2007


Undopack with congestion estimation:
The following download contains the work of Marvin Tom, David Leong, and David Yeager merged together into a single package. The contained version of VPR may be run as a standalone, separate from the Un/DoPack flow.

Download here ...

M. Tom, D. Leong, G. Lemieux, "Un/DoPack: Re-Clustering of Large System-on-Chip Designs with Interconnect Variation for Low-Cost FPGAs"
D. Leong, "Incremental Placement for Field-Programmable Gate Arrays"
D. Yeager, D. Chiu, G. Lemieux, "Congestion estimation and localization in fpgas: a visual tool for interconnect prediction"


In my spare time I have been known to go hiking/camping, play the occasional game of paintball, and more recently, indoor rock climbing. Winter activities usually include snowboarding.