Ameer M.S. Abdelhadi

Research Scientist / Hardware-Efficient Machine Learning
Department of Electrical and Computer Engineering
University of Toronto
Toronto, Ontario, M5S 3G4 Canada

e-mail:  ameer DOT abdelhadi AT utoronto DOT ca
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Publications

    Refereed Publications:

  1. A. M.S. Abdelhadi and H. Li,
    "Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs,"
    to appear in Proceedings of the 2021 International Conference on Field-Programmable Logic and Applications (FPL '2021), August 2021.
  2. H. Li, A. M.S. Abdelhadi, R. Shi, J. Zhang, and Q. Liu,
    "Adversarial Hardware with Functional and Topological Camouflage,"
    to appear in Proceedings of the 2021 IEEE International Symposium on Circuits and Systems (ISCAS '2021), May 2021.
  3. A. M.S. Abdelhadi and H. Li,
    "Reconfigurable Synthesizable Synchronization FIFOs,"
    to appear in Proceedings of the 2021 IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM '2021), May 2021.
  4. I. E. Vivancos, S. Sharify, D. Ly-Ma, A. M.S. Abdelhadi, C. Bannon, M. Nikolic, M. Mahmoud, A. D. Lascorz, G. Pekhimenko, and A. Moshovos,
    "Boveda: Building an On-Chip Deep Learning Memory Hierarchy Brick by Brick,"
    in Proceedings of the 2021 conference on Machine Learning and Systems (MLSys'2021), April 2021.
  5. H. Li, A. M.S. Abdelhadi, R. Shi, J. Zhang, and Q. Liu,
    "Adversarial Hardware with Functional and Topological Camouflage,"
    to appear in Transactions on Circuits and Systems II (TCAS-II), 2021.
  6. A. M.S. Abdelhadi,
    "Synthesizable Synchronization FIFOs Utilizing the Asynchronous Pulse-Based Handshake Protocol,"
    in Proceedings of the 2020 IEEE Nordic Circuits and Systems Conference (NorCAS'2020), October 2020.
  7. A. M.S. Abdelhadi,
    "High-Throughput Synthesizable Synchronization FIFOs for Mixed-Timing NoCs,"
    in Proceedings of the 53rd 2020 Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-53): 13th International Workshop on Network on Chip Architectures (NoCArc'2020), October 2020.
  8. A. M.S. Abdelhadi, C. S. Bouganis, and G. A. Constantinides,
    "Accelerated Approximate Nearest Neighbors Search Through Hierarchical Product Quantization,"
    in Proceedings of the 2019 International Conference on Field-Programmable Technology (ICFPT '2019), December 2019. [Paper: PDF, [Code: GitHub]
  9. A. M.S. Abdelhadi, and L. Shannon,
    "Revisiting Deep Learning Parallelism: Fine-Grained Inference Engine Utilizing Online Arithmetic,"
    in Proceedings of the 2019 International Conference on Field-Programmable Technology (ICFPT '2019), December 2019. [Paper: PDF, [Code: GitHub]
  10. A. M.S. Abdelhadi, Y. Zhang, D. Chen, G. Datta, P. Beerel, and M.R. Greenstreet
    "Two-Phase Asynchronous to Synchronous Interfaces with Early Synchronization for an Open-Source Bundled Data Flow,"
    in Proceedings of the 2019 IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC '2019), May 2019. [Paper: PDF]
  11. A. M.S. Abdelhadi, G. G.F. Lemieux, and L. Shannon,
    "Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories,"
    in Proceedings of the 2018 International Conference on Field-Programmable Logic and Applications (FPL '2018), August 2018.
    [Acceptance rate: 36/219=16.4%] [Paper: PDF, [Talk: PDF, PPT] [Code: GitHub]
  12. A. M.S. Abdelhadi, D. H. Noronha, S. J.E. Wilton, and L. Shannon,
    "Deep Neural Networks Benchmark Suite for FPGAs Utilizing a TensorFlow to Routing High-Level Synthesis ,"
    in Proceedings of the 2018 Computing Hardware for Emerging Intelligent Sensory Applications (COHESA), Toronto, Ontario, July 2018.
    [Paper: PDF, VSD]
  13. A. M.S. Abdelhadi and M. R. Greenstreet,
    "Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs,"
    in Proceedings of the 2017 IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC '2017), May 2017. (Best paper award winner)
    [Acceptance rate: 15/44=34%] [Paper: PDF] [Talk: PDF] [Code: GitHub]
  14. A. M.S. Abdelhadi and G. G.F. Lemieux,
    "A Multi-Ported Memory Compiler Utilizing True Dual-port BRAMs,"
    in Proceedings of the 2016 IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM '2016), May 2016. (Best paper candidate)
    [Acceptance rate: 18/93=19%] [Paper: PDF, DOI] [Talk: PDF, PPT] [Code: GitHub]
  15. A. M.S. Abdelhadi and G. G.F. Lemieux,
    "Modular Switched Multi-ported SRAM-based Memories,"
    ACM Transactions on Reconfigurable Technology and Systems (TRETS) Special Issue on Reconfigurable Components with Source Code, accepted in Jul. 2015. 27 pages. (Invited)
    [Paper: PDF] [Code: GitHub]
  16. A. M.S. Abdelhadi and G. G.F. Lemieux,
    "Modular SRAM-based Binary Content-Addressable Memories,"
    in Proceedings of the 2015 IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM '2015), May 2015.
    [Acceptance rate: 21/95=22%] [Paper: PDF, DOI] [Talk: PDF, PPT] [Code: GitHub]
  17. A. M.S. Abdelhadi and G. G.F. Lemieux,
    "Deep and Narrow Binary Content-Addressable Memories using FPGA-based BRAMs,"
    in Proceedings of the 2014 International Conference on Field-Programmable Technology (ICFPT '2014), December 2014.
    [Acceptance rate: 23/80=29%] [Paper: PDF, DOI] [Code: GitHub]
  18. A. M.S. Abdelhadi and G. G.F. Lemieux,
    "Modular Multi-Ported SRAM-based Memories,"
    in Proceedings of the 2014 ACM/SIGDA International Symposium on Field-programmable Gate Arrays (FPGA '2014), February 2014. (Best paper candidate)
    [Acceptance rate: 21/114=18%] [Paper: PDF, DOI] [Talk: PDF, PPT] [Code: GitHub]
  19. A. M.S. Abdelhadi, R. Ginosar, A. Kolodny, and E. G. Friedman,
    "Timing-Driven Variation-Aware Synthesis of Hybrid Mesh/Tree Clock Distribution Networks,"
    INTEGRATION, the VLSI journal (2013).
    [Paper: PDF, DOI] [Code: GitHub]
  20. A. Brant, A. M.S. Abdelhadi, A. Severance, T. Tang, M. Yue, and G. G.F. Lemieux,
    "Safe Overclocking of Tightly Coupled CGRAs and Processor Arrays using Razor,"
    in Proceedings of the 2013 IEEE intl. Conf. on Field-Programmable Custom Computing Machines (FCCM '2013), April 2013.
    [Acceptance rate: 19/110=17%] [Paper: PDF, DOI] [Talk: PDF, PPT] [Code: GitHub]
  21. A. M.S. Abdelhadi, T. Ono, B. Quinton, and M. R. Greenstreet,
    "Cell-based Modular mixed-timing Synchronizing FIFOs,"
    in Proceeding of the IEEE/ACM 2012 International Conference on Computer-Aided Design (ICCAD '12): Workshop on CAD for Multi-Synchronous and Asynchronous Circuits and Systems, San Jose, CA, November 2012.
    [Paper: PDF, [Code: GitHub]
  22. A. Brant, A. M.S. Abdelhadi, A. Severance, and G. G.F. Lemieux,
    "Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skew,"
    in Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT), December 2012.
    [Acceptance rate: 24/114=21%] [Paper: PDF, DOI] [Code: GitHub]
  23. A. M.S. Abdelhadi and G. G.F. Lemieux,
    "Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations,"
    in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (Reconfig), pp. 20-26, Dec. 2011.
    [Paper: PDF, DOI] [Talk: PDF, PPT] [Code: GitHub]
  24. A. M.S. Abdelhadi, R. Ginosar, A. Kolodny, and E. G. Friedman,
    "Synthesis of Variation-Aware Hybrid Clock Distribution Networks,"
    in Proceedings of the International Conference of the Israeli Semiconductor Industry (ChipEx '10), June 2010. [Paper: PDF]
  25. A. M.S. Abdelhadi, R. Ginosar, A. Kolodny, and E. G. Friedman,
    "Timing-Driven Variation-Aware Nonuniform Clock Mesh Synthesis,"
    in Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI '10), pp. 15-20, May 2010.
    [Acceptance rate: 50/165=30%] [Paper: PDF, DOI] [Talk: PDF, PPT] [Code: GitHub]
  26. Technical Reports:

  27. A. M.S. Abdelhadi
    "Teak: A Token-Flow Balsa Synthesizer - A Manual for Technion Users,"
    VLSI Systems Research Center, Department of Electrical Engineering, Technion - Israel Institute of Technology, Haifa, Israel, February 2011.
  28. A. M.S. Abdelhadi,
    "Self-timed handshake circuits synthesis with TiDE 5.2.12, Technion design flow,"
    VLSI Systems Research Center, Department of Electrical Engineering, Technion - Israel Institute of Technology, Haifa, Israel, November 2009.
  29. A. M.S. Abdelhadi,
    "Clock Distribution Issues for Network-on-Chip,"
    Department of Electrical Engineering, Technion - Israel Institute of Technology, Haifa, Israel, May 2008.
  30. Theses:

  31. A. M.S. Abdelhadi,
    "Architecture of Block-RAM-Based Massively Parallel Memory Structures: Multi-Ported Memories and Content-Addressable Memories,"
    Ph.D. Thesis with supervisor Prof. Guy Lemieux, Department of Electrical and Computer Engineering, University of British Columbia, September 2016.
    [Thesis: PDF, URI]
  32. A. M.S. Abdelhadi,
    "Timing-Driven Variation-Aware Hybrid Mesh/Tree Clock Distribution Network Synthesis,"
    M.Sc. Thesis with supervisors Prof. Eby Friedman (University of Rochester, USA), Prof. Ran Ginosar, and Prof. Avinoam Kolodny (Technion, Israel), Department of Electrical Engineering, Technion - Israel Institute of Technology, Haifa, Israel, December 2010.
    [Thesis: PDF, Abstract]
  33. A. M.S. Abdelhadi and A. Busool,
    "Out-of-order Asynchronous Synchronizer,"
    B.Sc. Thesis with supervisor Dr. Reuven Dobkin, Dept. of Electrical Engineering, Technion - Israel Institute of Technology, Haifa, Israel, July 2005.
    [Thesis: PDF]

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Last updated October 2020.
Copyright © 2020 Ameer M.S. Abdelhadi. All rights reserved.